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Integrated Circuits (ICs)

SN74F112NSR

Active
Texas Instruments

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET

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16 SO
Integrated Circuits (ICs)

SN74F112NSR

Active
Texas Instruments

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74F112NSR
Clock Frequency130 MHz
Current - Output High, Low [custom]1 mA
Current - Output High, Low [custom]20 mA
Current - Quiescent (Iq)19 mA
FunctionReset, Set(Preset)
Max Propagation Delay @ V, Max CL6.5 ns
Mounting TypeSurface Mount
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output TypeComplementary
Package / Case0.209 "
Package / Case16-SOIC
Package / Case5.3 mm
Supplier Device Package16-SO
Trigger TypeNegative Edge
TypeJK Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.93
10$ 0.82
25$ 0.77
100$ 0.63
250$ 0.58
500$ 0.49
1000$ 0.40
Digi-Reel® 1$ 0.93
10$ 0.82
25$ 0.77
100$ 0.63
250$ 0.58
500$ 0.49
1000$ 0.40
Tape & Reel (TR) 2000$ 0.36
6000$ 0.33
10000$ 0.32
Texas InstrumentsLARGE T&R 1$ 0.67
100$ 0.51
250$ 0.38
1000$ 0.27

Description

General part information

SN74F112 Series

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.

The SN74F112 is characterized for operation from 0°C to 70°C.

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.