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SN74F112

SN74F112 Series

Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset

Manufacturer: Texas Instruments

Catalog

Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset

Key Features

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPsPackage Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

Description

AI
The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high. The SN74F112 is characterized for operation from 0°C to 70°C. The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high. The SN74F112 is characterized for operation from 0°C to 70°C.