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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74F112NG4 |
|---|---|
| Clock Frequency | 130 MHz |
| Current - Output High, Low [custom] | 1 mA |
| Current - Output High, Low [custom] | 20 mA |
| Current - Quiescent (Iq) | 19 mA |
| Function | Reset, Set(Preset) |
| Max Propagation Delay @ V, Max CL | 6.5 ns |
| Mounting Type | Through Hole |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Complementary |
| Package / Case | 0.3 in |
| Package / Case | 16-DIP |
| Package / Case | 7.62 mm |
| Supplier Device Package | 16-PDIP |
| Trigger Type | Negative Edge |
| Type | JK Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1125 | $ 0.36 | |
Description
General part information
SN74F112 Series
The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.
The SN74F112 is characterized for operation from 0°C to 70°C.
The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.
Documents
Technical documentation and resources
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