SN74F112D
ObsoleteDUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
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SN74F112D
ObsoleteDUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74F112D |
|---|---|
| Clock Frequency | 130 MHz |
| Current - Output High, Low [custom] | 1 mA |
| Current - Output High, Low [custom] | 20 mA |
| Current - Quiescent (Iq) | 19 mA |
| Function | Reset, Set(Preset) |
| Max Propagation Delay @ V, Max CL | 6.5 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Complementary |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 16-SOIC |
| Trigger Type | Negative Edge |
| Type | JK Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Arrow | N/A | 1 | $ 0.13 | |
| Digikey | Tube | 1 | $ 1.48 | |
| 10 | $ 1.33 | |||
| 40 | $ 1.26 | |||
| 120 | $ 1.03 | |||
| 280 | $ 0.97 | |||
| 520 | $ 0.85 | |||
| Texas Instruments | TUBE | 1 | $ 1.10 | |
| 100 | $ 0.85 | |||
| 250 | $ 0.62 | |||
| 1000 | $ 0.45 | |||
Description
General part information
SN74F112 Series
The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.
The SN74F112 is characterized for operation from 0°C to 70°C.
The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.
Documents
Technical documentation and resources
