74ABT84110-Bit Bus-Interface D-Type Latches With 3-State Outputs | Integrated Circuits (ICs) | 10 | Active | The SN54ABT841 and SN74ABT841A 10-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The ten transparent D-type latches provide true data at their outputs.
A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT841 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT841A is characterized for operation from -40°C to 85°C.
The SN54ABT841 and SN74ABT841A 10-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The ten transparent D-type latches provide true data at their outputs.
A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT841 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT841A is characterized for operation from -40°C to 85°C. |
74ABT8439-Bit Bus-Interface D-Type Latches With 3-State Outputs | Logic | 7 | Active | The 'ABT843 9-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The nine transparent D-type latches provide true data at the outputs.
A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT843 is characterized for operation from -40°C to 85°C.
The 'ABT843 9-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The nine transparent D-type latches provide true data at the outputs.
A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT843 is characterized for operation from -40°C to 85°C. |
74ABT8538-Bit To 9-Bit Parity Bus Transceivers | Logic | 4 | Active | 8-Bit To 9-Bit Parity Bus Transceivers |
| Integrated Circuits (ICs) | 5 | Active | |
74ABT86110-Bit Transceivers With 3-State Outputs | Buffers, Drivers, Receivers, Transceivers | 4 | Active | The 'ABT861 are 10-bit transceivers designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing.
These devices allow noninverted data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic levels at the output-enable (OEAB\ and OEBA\) inputs.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT861 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT861 is characterized for operation from -40°C to 85°C.
The 'ABT861 are 10-bit transceivers designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing.
These devices allow noninverted data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic levels at the output-enable (OEAB\ and OEBA\) inputs.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT861 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT861 is characterized for operation from -40°C to 85°C. |
| Buffers, Drivers, Receivers, Transceivers | 1 | Obsolete | |
| Specialty Logic | 4 | Active | |
| Integrated Circuits (ICs) | 5 | Active | |
| Integrated Circuits (ICs) | 3 | Obsolete | |
| Specialty Logic | 4 | Active | |
