T
Texas Instruments
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Part | Spec A | Spec B | Spec C | Spec D | Description |
|---|---|---|---|---|---|
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Part | Spec A | Spec B | Spec C | Spec D | Description |
|---|---|---|---|---|---|
| Part | Category | Description |
|---|---|---|
Texas Instruments | Integrated Circuits (ICs) | BUS DRIVER, BCT/FBT SERIES |
Texas Instruments | Integrated Circuits (ICs) | 12BIT 3.3V~3.6V 210MHZ PARALLEL VQFN-48-EP(7X7) ANALOG TO DIGITAL CONVERTERS (ADC) ROHS |
Texas Instruments | Integrated Circuits (ICs) | TMX320DRE311 179PIN UBGA 200MHZ |
Texas Instruments TPS61040DRVTG4Unknown | Integrated Circuits (ICs) | IC LED DRV RGLTR PWM 350MA 6WSON |
Texas Instruments LP3876ET-2.5Obsolete | Integrated Circuits (ICs) | IC REG LINEAR 2.5V 3A TO220-5 |
Texas Instruments LMS1585ACSX-ADJObsolete | Integrated Circuits (ICs) | IC REG LIN POS ADJ 5A DDPAK |
Texas Instruments INA111APG4Obsolete | Integrated Circuits (ICs) | IC INST AMP 1 CIRCUIT 8DIP |
Texas Instruments | Integrated Circuits (ICs) | AUTOMOTIVE, QUAD 36V 1.2MHZ OPERATIONAL AMPLIFIER |
Texas Instruments OPA340NA/3KG4Unknown | Integrated Circuits (ICs) | IC OPAMP GP 1 CIRCUIT SOT23-5 |
Texas Instruments PT5112AObsolete | Power Supplies - Board Mount | DC DC CONVERTER 8V 8W |
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
DS30BA1013.125-Gbps differential buffer | Integrated Circuits (ICs) | 3 | Active | The DS30BA101 is a high-speed differential buffer for cable driving, signal buffering, and signal repeating applications. Its fully differential signal path ensures exceptional signal integrity and noise immunity. The DS30BA101 drives both differential and single-ended transmission lines at data rates up to 3.125 Gbps.
The output voltage amplitude is adjustable via a single external resistor for cable driving applications into 75Ω single-ended and 100Ω differential mode impedances.
The DS30BA101 is powered from a single 3.3V supply and consumes 165 mW (typical). It operates over the full industrial temperature range of -40°C to +85°C and is available in a 4 x 4 mm 16-pin WQFN package.
The DS30BA101 is a high-speed differential buffer for cable driving, signal buffering, and signal repeating applications. Its fully differential signal path ensures exceptional signal integrity and noise immunity. The DS30BA101 drives both differential and single-ended transmission lines at data rates up to 3.125 Gbps.
The output voltage amplitude is adjustable via a single external resistor for cable driving applications into 75Ω single-ended and 100Ω differential mode impedances.
The DS30BA101 is powered from a single 3.3V supply and consumes 165 mW (typical). It operates over the full industrial temperature range of -40°C to +85°C and is available in a 4 x 4 mm 16-pin WQFN package. |
DS30EA1010.15-to-3.125 Gbps adaptive cable equalizer | Integrated Circuits (ICs) | 1 | Active | The DS30EA101 is an adaptive cable equalizer optimized for equalizing data transmitted over copper cables. The equalizer operates over a range of data rates from 150 Mbps to 3.125 Gbps and automatically adapts to equalize signals sent over any cable length from zero meters to lengths that attenuate the signal by 50 dB at 1.5 GHz.
The DS30EA101 allows either single-ended or differential input. This enables equalization of signals over coaxial cables as well as twisted pair cables.
Additional features include an LOS detect and output enable which, when tied together, disable the output when no input signal is present.
The DS30EA101 is powered from a single 2.5V supply and consumes 115 mW (typical). It operates over the full industrial temperature range of -40°C to +85°C and is available in a 4 x 4 mm 16-pin WQFN package.
The DS30EA101 is an adaptive cable equalizer optimized for equalizing data transmitted over copper cables. The equalizer operates over a range of data rates from 150 Mbps to 3.125 Gbps and automatically adapts to equalize signals sent over any cable length from zero meters to lengths that attenuate the signal by 50 dB at 1.5 GHz.
The DS30EA101 allows either single-ended or differential input. This enables equalization of signals over coaxial cables as well as twisted pair cables.
Additional features include an LOS detect and output enable which, when tied together, disable the output when no input signal is present.
The DS30EA101 is powered from a single 2.5V supply and consumes 115 mW (typical). It operates over the full industrial temperature range of -40°C to +85°C and is available in a 4 x 4 mm 16-pin WQFN package. |
DS320PR1601PCIe® 5.0, 32-Gbps, 16-lane linear redriver | Signal Buffers, Repeaters, Splitters | 2 | Active | The DS320PR1601 is a 32-channel (16-channel in each direction) or x16 (16-lane) low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0 and other interfaces up to 32 Gbps.
The DS320PR1601 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear datapaths of DS320PR1601 preserves transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its equalization.
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The DS320PR1601 is a 32-channel (16-channel in each direction) or x16 (16-lane) low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0 and other interfaces up to 32 Gbps.
The DS320PR1601 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear datapaths of DS320PR1601 preserves transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its equalization.
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DS320PR410PCIe® 5.0, 32-Gbps, 4-channel linear redriver | Integrated Circuits (ICs) | 2 | Active | The DS320PR410 is a four-channel low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0, and other interfaces up to 32 Gbps.
The DS320PR410 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear data-paths of DS320PR410 preserve transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its useful equalization.
The DS320PR410 is a four-channel low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0, and other interfaces up to 32 Gbps.
The DS320PR410 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear data-paths of DS320PR410 preserve transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its useful equalization. |
DS320PR810PCIe® 5.0, 32-Gbps, 8-channel linear redriver | Integrated Circuits (ICs) | 1 | Active | The DS320PR 810 is a n eight channel low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0, and other interfaces up to 32 Gbps.
The DS320PR 810 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear data-paths of DS320PR 810 preserve transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its useful equalization. The data-path of the device uses an internally regulated power rail that provides high immunity to any supply noise on the board.
The device also has low AC and DC gain variation providing consistent equalization in high volume platform deployment.
The DS320PR 810 is a n eight channel low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0, and other interfaces up to 32 Gbps.
The DS320PR 810 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear data-paths of DS320PR 810 preserve transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its useful equalization. The data-path of the device uses an internally regulated power rail that provides high immunity to any supply noise on the board.
The device also has low AC and DC gain variation providing consistent equalization in high volume platform deployment. |
DS320PR822PCIe® 5.0, 32-Gbps, 8-channel linear redriver with four 2x2 crosspoint multiplexers | Integrated Circuits (ICs) | 1 | Active | The DS320PR 822 is a low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0, and other interfaces up to 32 Gbps. The DS320PR 822 provides four 2x2 cross-point mux functionality.
The DS320PR 822 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear data-paths of DS320PR 822 preserve transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its useful equalization. The data-path of the device uses an internally regulated power rail that provides high immunity to any supply noise on the board.
The device also has low AC and DC gain variation providing consistent equalization in high volume platform deployment.
The DS320PR 822 is a low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0, and other interfaces up to 32 Gbps. The DS320PR 822 provides four 2x2 cross-point mux functionality.
The DS320PR 822 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear data-paths of DS320PR 822 preserve transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its useful equalization. The data-path of the device uses an internally regulated power rail that provides high immunity to any supply noise on the board.
The device also has low AC and DC gain variation providing consistent equalization in high volume platform deployment. |
DS32EL0124125 to 312.5-MHz FPGA-link deserializer with DDR LVDS parallel interface | Integrated Circuits (ICs) | 3 | Active | The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.
The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins. |
DS32EL0421125 to 312.5-MHz FPGA-link serializer with DDR LVDS parallel interface | Interface | 2 | Active | The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.
The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins. |
DS32ELX0124125 to 312.5-MHz FPGA-link deserializer with DDR LVDS parallel interface | Integrated Circuits (ICs) | 2 | Active | The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.
The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins. |
DS32ELX0421125 to 312.5-MHz FPGA-link serializer with DDR LVDS parallel interface | Interface | 2 | Active | The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.
The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins. |