DS32ELX0124 Series
125 to 312.5-MHz FPGA-link deserializer with DDR LVDS parallel interface
Manufacturer: Texas Instruments
Catalog
125 to 312.5-MHz FPGA-link deserializer with DDR LVDS parallel interface
Key Features
• 5-bit DDR LVDS Parallel Data InterfaceProgrammable Receive EqualizationSelectable DC-Balance DecoderSelectable De-ScramblerRemote Sense for Automatic Detection and Negotiation of Link StatusNo External Receiver Reference Clock RequiredLVDS Parallel InterfaceProgrammable LVDS Output Clock DelaySupports Output Data-Valid SignalingSupports Keep-Alive Clock OutputOn Chip LC VCOsRedundant Serial Input (ELX device only)Retimed Serial Output (ELX device only)Configurable PLL Loop BandwidthConfigurable via SMBusLoss of Lock and Error Reporting48-pin WQFN Package with Exposed DAPKey Specifications1.25 to 3.125 Gbps Serial Data Rate125 to 312.5 MHz DDR Parallel Clock-40° to +85°C Temperature Range> 8 kV ESD (HBM) Protection0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)All trademarks are the property of their respective owners.5-bit DDR LVDS Parallel Data InterfaceProgrammable Receive EqualizationSelectable DC-Balance DecoderSelectable De-ScramblerRemote Sense for Automatic Detection and Negotiation of Link StatusNo External Receiver Reference Clock RequiredLVDS Parallel InterfaceProgrammable LVDS Output Clock DelaySupports Output Data-Valid SignalingSupports Keep-Alive Clock OutputOn Chip LC VCOsRedundant Serial Input (ELX device only)Retimed Serial Output (ELX device only)Configurable PLL Loop BandwidthConfigurable via SMBusLoss of Lock and Error Reporting48-pin WQFN Package with Exposed DAPKey Specifications1.25 to 3.125 Gbps Serial Data Rate125 to 312.5 MHz DDR Parallel Clock-40° to +85°C Temperature Range> 8 kV ESD (HBM) Protection0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)All trademarks are the property of their respective owners.
Description
AI
The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.
The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.
