Texas Instruments

The DS26LS31MQML is a quad differential line driver designed for digital data transmission over balanced lines. The DS26LS31MQML meets all the requirements of EIA Standard RS-422 and Federal Standard 1020. It is designed to provide unipolar differential drive to twisted-pair or parallel-wire transmission lines. The circuit provides an enable and disable function common to all four drivers. The DS26LS31MQML features TRI-STATE outputs and logically ANDed complementary outputs. The inputs are all LS compatible and are all one unit load. The DS26LS31 features a power up/down protection circuit which keeps the output in a high impedance state (TRI-STATE) during power up or down preventing erroneous glitches on the transmission lines. The DS26LS31MQML is a quad differential line driver designed for digital data transmission over balanced lines. The DS26LS31MQML meets all the requirements of EIA Standard RS-422 and Federal Standard 1020. It is designed to provide unipolar differential drive to twisted-pair or parallel-wire transmission lines. The circuit provides an enable and disable function common to all four drivers. The DS26LS31MQML features TRI-STATE outputs and logically ANDed complementary outputs. The inputs are all LS compatible and are all one unit load. The DS26LS31 features a power up/down protection circuit which keeps the output in a high impedance state (TRI-STATE) during power up or down preventing erroneous glitches on the transmission lines.

The DS26LV32A is a high speed quad differential CMOS receiver that is comparable to TIA/EIA-422-B and ITU-T V.11 standards, but with a specified common mode voltage range of -0.5V to +5.5V due to the lower operating supply voltage of 3.0V to 3.6V. The TRI-STATE enables, EN andEN, allow the device to be active High or active Low. The enables are common to all four receivers. The receiver output (RO) is specified to be High when the inputs are left open. The receiver can detect signals as low as ±200mV over the common mode range of -0.5V to +5.5V. The receiver outputs (RO) are compatible with TTL and LVCMOS levels. The DS26LV32A is a high speed quad differential CMOS receiver that is comparable to TIA/EIA-422-B and ITU-T V.11 standards, but with a specified common mode voltage range of -0.5V to +5.5V due to the lower operating supply voltage of 3.0V to 3.6V. The TRI-STATE enables, EN andEN, allow the device to be active High or active Low. The enables are common to all four receivers. The receiver output (RO) is specified to be High when the inputs are left open. The receiver can detect signals as low as ±200mV over the common mode range of -0.5V to +5.5V. The receiver outputs (RO) are compatible with TTL and LVCMOS levels.

The DS280BR810 is an extremely low-power, high-performance eight-channel linear equalizer supporting multi-rate, multi-protocol interfaces up to 28 Gbps. It is used to extend the reach and improve the robustness of high-speed serial links for front-port, backplane, and chip-to-chip applications. The linear nature of the DS280BR810’s equalization preserves the transmit signal characteristics, thereby allowing the host and link partner ASICs to freely negotiate transmit equalizer coefficients (100 G-CR4/KR4). This transparency to the link training protocol facilitates system-level interoperability with minimal effect on the latency. Each channel operates independently, which allows the DS280BR810 to support individual lane Forward Error Correction (FEC) pass-through. The DS280BR810’s small package dimensions, optimized high-speed signal escape, and the pin-compatible retimer portfolio make the DS280BR810 ideal for high-density backplane applications. Simplified equalization control, low power consumption, and ultra-low additive jitter make it suitable for front-port interfaces such as 100 G-SR4/LR4/CR4. The small 8-mm x 13-mm footprint easily fits behind numerous standard front-port connectors like QSFP28, SFP28, CFP2/CFP4, and CDFP without the need for a heat sink. Integrated AC coupling capacitors (RX and TX) eliminate the need for external capacitors on the PCB. The DS280BR810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and bill of materials (BOM) cost. A pin-compatible retimer device is available for longer reach applications. The DS280BR810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. The DS280BR810 is an extremely low-power, high-performance eight-channel linear equalizer supporting multi-rate, multi-protocol interfaces up to 28 Gbps. It is used to extend the reach and improve the robustness of high-speed serial links for front-port, backplane, and chip-to-chip applications. The linear nature of the DS280BR810’s equalization preserves the transmit signal characteristics, thereby allowing the host and link partner ASICs to freely negotiate transmit equalizer coefficients (100 G-CR4/KR4). This transparency to the link training protocol facilitates system-level interoperability with minimal effect on the latency. Each channel operates independently, which allows the DS280BR810 to support individual lane Forward Error Correction (FEC) pass-through. The DS280BR810’s small package dimensions, optimized high-speed signal escape, and the pin-compatible retimer portfolio make the DS280BR810 ideal for high-density backplane applications. Simplified equalization control, low power consumption, and ultra-low additive jitter make it suitable for front-port interfaces such as 100 G-SR4/LR4/CR4. The small 8-mm x 13-mm footprint easily fits behind numerous standard front-port connectors like QSFP28, SFP28, CFP2/CFP4, and CDFP without the need for a heat sink. Integrated AC coupling capacitors (RX and TX) eliminate the need for external capacitors on the PCB. The DS280BR810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and bill of materials (BOM) cost. A pin-compatible retimer device is available for longer reach applications. The DS280BR810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM.

The DS280BR820 is an extremely low-power, high-performance eight-channel linear equalizer supporting multi-rate, multi-protocol interfaces up to 28 Gbps. It is used to extend the reach and improve the robustness of high-speed serial links for backplane, front-port, and chip-to-chip applications. The linear nature of the DS280BR820’s equalization preserves the transmit signal characteristics, thereby allowing the host and link partner ASICs to freely negotiate transmit equalizer coefficients (100G-CR4/KR4). This transparency to the link training protocol facilitates system-level interoperability with minimal effect on the latency. Each channel operates independently, which allows the DS280BR820 to support individual lane Forward Error Correction (FEC) pass-through. The DS280BR820’s small package dimensions, optimized high-speed signal escape, and the pin-compatible Retimer portfolio make the DS280BR820 ideal for high-density backplane applications. Simplified equalization control, low power consumption, and ultra-low additive jitter make it suitable for front-port interfaces such as 100G-SR4/LR4/CR4. The small 8-mm x 13-mm footprint easily fits behind numerous standard front-port connectors like QSFP, SFP, CFP2, CFP4, and CDFP without the need for a heat sink. Integrated AC coupling capacitors (RX side) eliminate the need for external capacitors on the PCB. The DS280BR820 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and bill of materials (BOM) cost. A pin-compatible Retimer device is available for longer reach applications. The DS280BR820 can be configured either through the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. The DS280BR820 is an extremely low-power, high-performance eight-channel linear equalizer supporting multi-rate, multi-protocol interfaces up to 28 Gbps. It is used to extend the reach and improve the robustness of high-speed serial links for backplane, front-port, and chip-to-chip applications. The linear nature of the DS280BR820’s equalization preserves the transmit signal characteristics, thereby allowing the host and link partner ASICs to freely negotiate transmit equalizer coefficients (100G-CR4/KR4). This transparency to the link training protocol facilitates system-level interoperability with minimal effect on the latency. Each channel operates independently, which allows the DS280BR820 to support individual lane Forward Error Correction (FEC) pass-through. The DS280BR820’s small package dimensions, optimized high-speed signal escape, and the pin-compatible Retimer portfolio make the DS280BR820 ideal for high-density backplane applications. Simplified equalization control, low power consumption, and ultra-low additive jitter make it suitable for front-port interfaces such as 100G-SR4/LR4/CR4. The small 8-mm x 13-mm footprint easily fits behind numerous standard front-port connectors like QSFP, SFP, CFP2, CFP4, and CDFP without the need for a heat sink. Integrated AC coupling capacitors (RX side) eliminate the need for external capacitors on the PCB. The DS280BR820 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and bill of materials (BOM) cost. A pin-compatible Retimer device is available for longer reach applications. The DS280BR820 can be configured either through the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM.

The DS280DF810 is an eight-channel multi-rate Retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired high-speed serial links while achieving a bit error rate (BER) of 10-15 or less. Each channel of the DS280DF810 independently locks to serial data rates in a continuous range from 20.2Gbps to 28.4Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.1376Gbps, 10.3125Gbps, and 12.5Gbps, which allows the DS280DF810 to support individual lane Forward Error Correction (FEC) pass-through. Integrated physical AC coupling capacitors (TX and RX) eliminate the need for external capacitors on the PCB. The DS280DF810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and BOM cost. The advanced equalization features of the DS280DF810 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is an excellent choice for front-port optical module applications to reset the jitter budget and retimer the high-speed serial data. The DS280DF810 implements 2x2 cross-point on each channel pair, providing the host with both lane crossing and fanout options. The DS280DF810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. A non-disruptive on-chip eye monitor and a PRBS generator and checker allow for in-system diagnostics. The DS280DF810 is an eight-channel multi-rate Retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired high-speed serial links while achieving a bit error rate (BER) of 10-15 or less. Each channel of the DS280DF810 independently locks to serial data rates in a continuous range from 20.2Gbps to 28.4Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.1376Gbps, 10.3125Gbps, and 12.5Gbps, which allows the DS280DF810 to support individual lane Forward Error Correction (FEC) pass-through. Integrated physical AC coupling capacitors (TX and RX) eliminate the need for external capacitors on the PCB. The DS280DF810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and BOM cost. The advanced equalization features of the DS280DF810 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is an excellent choice for front-port optical module applications to reset the jitter budget and retimer the high-speed serial data. The DS280DF810 implements 2x2 cross-point on each channel pair, providing the host with both lane crossing and fanout options. The DS280DF810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. A non-disruptive on-chip eye monitor and a PRBS generator and checker allow for in-system diagnostics.

The DS280MB810 is an extremely low-power, high-performance eight-channel linear equalizer supporting multi-rate, multi-protocol interfaces up to 28 Gbaud NRZ. It is used to extend the reach and improve the robustness of high-speed serial links for backplane, front-port, and chip-to-chip applications. The DS280MB810 includes a full 2x2 cross-point switch between each pair of adjacent channels which enables 2-to-1 multiplexing and 1-to-2 de-multiplexing applications for failover redundancy, as well as signal cross-over to aid PCB routing. The cross-point can be controlled through pins or the SMBus register interface. The linear nature of the DS280MB810’s equalization preserves the transmit signal characteristics, thereby allowing the host and link partner ASICs to freely negotiate transmit equalizer coefficients (100G-CR4/KR4). This transparency to the link training protocol facilitates system-level interoperability with minimal effect on the latency. The DS280MB810 supports two-level pulse amplitude modulation (PAM), or NRZ, for symbol rates up to 28 Gbaud and peak signal amplitude within the linear operating range. Each channel operates independently, and every channel can be configured uniquely. In most application scenarios, the same configuration can be used regardless of data rate. The DS280MB810’s small package dimensions, optimized high-speed signal escape, and the pin-compatible Retimer portfolio make the DS280MB810 ideal for high-density backplane applications. Simplified equalization control, low power consumption, and ultra-low additive jitter make it suitable for front-port interfaces such as 100G-SR4/LR4/CR4. The small 8-mm x 13-mm footprint easily fits behind numerous standard front-port connectors like QSFP, SFP, CFP, and CDFP without the need for a heat sink. The DS280MB810 is an extremely low-power, high-performance eight-channel linear equalizer supporting multi-rate, multi-protocol interfaces up to 28 Gbaud NRZ. It is used to extend the reach and improve the robustness of high-speed serial links for backplane, front-port, and chip-to-chip applications. The DS280MB810 includes a full 2x2 cross-point switch between each pair of adjacent channels which enables 2-to-1 multiplexing and 1-to-2 de-multiplexing applications for failover redundancy, as well as signal cross-over to aid PCB routing. The cross-point can be controlled through pins or the SMBus register interface. The linear nature of the DS280MB810’s equalization preserves the transmit signal characteristics, thereby allowing the host and link partner ASICs to freely negotiate transmit equalizer coefficients (100G-CR4/KR4). This transparency to the link training protocol facilitates system-level interoperability with minimal effect on the latency. The DS280MB810 supports two-level pulse amplitude modulation (PAM), or NRZ, for symbol rates up to 28 Gbaud and peak signal amplitude within the linear operating range. Each channel operates independently, and every channel can be configured uniquely. In most application scenarios, the same configuration can be used regardless of data rate. The DS280MB810’s small package dimensions, optimized high-speed signal escape, and the pin-compatible Retimer portfolio make the DS280MB810 ideal for high-density backplane applications. Simplified equalization control, low power consumption, and ultra-low additive jitter make it suitable for front-port interfaces such as 100G-SR4/LR4/CR4. The small 8-mm x 13-mm footprint easily fits behind numerous standard front-port connectors like QSFP, SFP, CFP, and CDFP without the need for a heat sink.