DS32ELX0421 Series

125 to 312.5-MHz FPGA-link serializer with DDR LVDS parallel interface

Catalog

125 to 312.5-MHz FPGA-link serializer with DDR LVDS parallel interface

Part	Output Type	Function	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply	Input Type	Mounting Type	Number of Outputs	Qualification	Grade	Package / Case	Supplier Device Package	Number of Inputs
Texas Instruments DS32ELX0421SQ/NOPB	1.81 mOhm	Serializer	85 °C	-40 °C	2.5 V 3.3 V	LVDS	Surface Mount	2	AEC-Q100	Automotive	48-WFQFN Exposed Pad	48-WQFN (7x7)	5
Texas Instruments DS32ELX0421SQE/NOPB	1.81 mOhm	Serializer	85 °C	-40 °C	2.5 V 3.3 V	LVDS	Surface Mount	2	AEC-Q100	Automotive	48-WFQFN Exposed Pad	48-WQFN (7x7)	5

Catalog

125 to 312.5-MHz FPGA-link serializer with DDR LVDS parallel interface

Key Features

• 5-bit DDR LVDS Parallel Data InterfaceProgrammable Transmit De-emphasisConfigurable Output Levels (VOD)Selectable DC-balanced EncoderSelectable Data ScramblerRemote Sense for Automatic Detection and Negotiation of Link StatusOn Chip LC VCOsRedundant Serial Output (ELX device only)Data Valid Signaling to Assist with Synchronization of Multiple ReceiversSupports AC- and DC-coupled SignalingIntegrated CML and LVDS TerminationsConfigurable PLL Loop BandwidthProgrammable Output Termination (50Ω or 75Ω).Built-in Test Pattern GeneratorLoss of Lock and Error ReportingConfigurable via SMBus48-pin WQFN Package with Exposed DAPKey Specifications1.25 to 3.125 Gbps Serial Data Rate125 to 312.5 MHz DDR Parallel Clock-40° to +85°C Temperature Range>8 kV ESD (HBM) ProtectionLow Intrinsic Jitter — 35ps at 3.125 GbpsAll trademarks are the property of their respective owners.5-bit DDR LVDS Parallel Data InterfaceProgrammable Transmit De-emphasisConfigurable Output Levels (VOD)Selectable DC-balanced EncoderSelectable Data ScramblerRemote Sense for Automatic Detection and Negotiation of Link StatusOn Chip LC VCOsRedundant Serial Output (ELX device only)Data Valid Signaling to Assist with Synchronization of Multiple ReceiversSupports AC- and DC-coupled SignalingIntegrated CML and LVDS TerminationsConfigurable PLL Loop BandwidthProgrammable Output Termination (50Ω or 75Ω).Built-in Test Pattern GeneratorLoss of Lock and Error ReportingConfigurable via SMBus48-pin WQFN Package with Exposed DAPKey Specifications1.25 to 3.125 Gbps Serial Data Rate125 to 312.5 MHz DDR Parallel Clock-40° to +85°C Temperature Range>8 kV ESD (HBM) ProtectionLow Intrinsic Jitter — 35ps at 3.125 GbpsAll trademarks are the property of their respective owners.

Description

The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface. The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps. The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path. The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins. The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface. The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps. The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path. The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.