DS110DF4108.5 to 11.3-Gbps quad channel retimer with adaptive EQ, CDR and DFE | Specialized | 1 | Active | The DS110DF410 is a four channel retimer with integrated signal conditioning. The device includes a fully adaptive Continuous-Time Linear Equalizer (CTLE), self calibrating 5-tap Decision Feedback Equalizer (DFE), Clock and Data Recovery (CDR), and transmit De-Emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1×10–15.
Each channel can independently lock to data rates from 8.5 to 11.3 Gbps, and associated sub rates (div by 2, 4 and 8) to support a variety of communication protocols. A 25-MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.
The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.
The DS110DF410 is a four channel retimer with integrated signal conditioning. The device includes a fully adaptive Continuous-Time Linear Equalizer (CTLE), self calibrating 5-tap Decision Feedback Equalizer (DFE), Clock and Data Recovery (CDR), and transmit De-Emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1×10–15.
Each channel can independently lock to data rates from 8.5 to 11.3 Gbps, and associated sub rates (div by 2, 4 and 8) to support a variety of communication protocols. A 25-MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.
The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning. |
DS110RT4108.5 to 11.3-Gbps quad channel retimer with adaptive EQ and CDR | Interface | 2 | Active | The DS110RT410 is a four-channel retimer with integrated signal conditioning. The device includes a fully adaptive continuous-time linear equalizer (CTLE), clock and data recovery (CDR), and a transmit de-emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1 × 10–15. For channels with a high amount of crosstalk, the DS110DF410 should be used because it has self-calibrating 5-tap decision-feedback equalizer (DFE).
Each channel can independently lock to data rates from 8.5 to 11.3 Gbps, and associated sub-rates (divide by 2, 4, and 8) to support a variety of communication protocols. A 25-MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.
The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded through an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.
The DS110RT410 is a four-channel retimer with integrated signal conditioning. The device includes a fully adaptive continuous-time linear equalizer (CTLE), clock and data recovery (CDR), and a transmit de-emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1 × 10–15. For channels with a high amount of crosstalk, the DS110DF410 should be used because it has self-calibrating 5-tap decision-feedback equalizer (DFE).
Each channel can independently lock to data rates from 8.5 to 11.3 Gbps, and associated sub-rates (divide by 2, 4, and 8) to support a variety of communication protocols. A 25-MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.
The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded through an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning. |
| Development Boards, Kits, Programmers | 4 | Active | |
DS125BR11112.5-Gbps 2-channel redrivers with input equalization | Integrated Circuits (ICs) | 1 | Active | The DS125BR111 is an extremely low power high performance repeater/redriver designed to support 1-lane carrying high speed interface up to 12.5 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of 3-10 dB at 6 GHz in each channel. When operating in SAS-3 or PCIe Gen-3 applications, the DS125BR111 preserves transmit signal characteristics allowing the host controller and the end point to negotiate transmit equalizer coefficients. Transparency to the link training protocol maximizes the flexibility of the physical placement of the device within the interconnect and improves overall channel performance.
The programmable settings can be applied easily via pins, software (SMBus or I2C), or loaded via an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.
The DS125BR111 is an extremely low power high performance repeater/redriver designed to support 1-lane carrying high speed interface up to 12.5 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of 3-10 dB at 6 GHz in each channel. When operating in SAS-3 or PCIe Gen-3 applications, the DS125BR111 preserves transmit signal characteristics allowing the host controller and the end point to negotiate transmit equalizer coefficients. Transparency to the link training protocol maximizes the flexibility of the physical placement of the device within the interconnect and improves overall channel performance.
The programmable settings can be applied easily via pins, software (SMBus or I2C), or loaded via an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver. |
| Evaluation and Demonstration Boards and Kits | 2 | Active | The DS125BR401A is an extremely low-power high-performance repeater/redriver designed to support four lanes carrying high speed interface up to 12 Gbps. The B-Side receiver’s continuous time linear equalizers (CTLE) provide high frequency boost of up to +24 dB at 6 GHz (12 Gbps) and are capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as backplane traces or twinaxial copper cables. The programmable equalization allows maximum flexibility in the physical placement within the interconnect channel. The A-Side channel has a 10 dB linear equalizer and linear output driver.
The A-Side channel has a settable 3-10 dB linear equalizer coupled to a linear output driver. When operating in SAS-3 and PCIe Gen-3 applications the DS125BR401A preserves transmit signal characteristics allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency to the link training protocol aides system level interoperability and minimum latency.
The programmable settings can be applied easily via Terminals, software (SMBus or I2C), or loaded via an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.
The DS125BR401A is an extremely low-power high-performance repeater/redriver designed to support four lanes carrying high speed interface up to 12 Gbps. The B-Side receiver’s continuous time linear equalizers (CTLE) provide high frequency boost of up to +24 dB at 6 GHz (12 Gbps) and are capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as backplane traces or twinaxial copper cables. The programmable equalization allows maximum flexibility in the physical placement within the interconnect channel. The A-Side channel has a 10 dB linear equalizer and linear output driver.
The A-Side channel has a settable 3-10 dB linear equalizer coupled to a linear output driver. When operating in SAS-3 and PCIe Gen-3 applications the DS125BR401A preserves transmit signal characteristics allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency to the link training protocol aides system level interoperability and minimum latency.
The programmable settings can be applied easily via Terminals, software (SMBus or I2C), or loaded via an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver. |
DS125BR800A12.5-Gbps 8-channel redriver with input CTLE and output De-Emphasis | Signal Buffers, Repeaters, Splitters | 3 | Active | The DS125BR800A is an extremely low-power high-performance multi-protocol repeater/redriver designed to support eight channels of PCIe, SAS, and other high-speed interface serial protocols up to 12.5 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of up to +30 dB at 6.25 GHz (12.5 Gbps) in each of its eight channels and is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as 30in+ backplane traces or 8m+ copper cables, hence enabling host controllers to ensure an error free end-to-end link. The strong linear equalization maximizes interconnect channel extension when the DS125BR800A is placed with the majority of channel loss on the devices input side. Adjustable transmit de-emphasis and output voltage amplitude help to compensate for the remaining channel attenuation on the output side.
When operating in SAS-3 and PCIe Gen-3 mode, the DS125BR800A transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency. With a low power consumption of 65 mW/channel (typ) and option to turn-off unused channels, the DS125BR800A enables energy efficient system design. A single supply of 3.3 V or 2.5 V is required to power the device.
The programmable settings can be applied easily via pins, software (SMBus or I2C) or loaded via an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.
The DS125BR800A is an extremely low-power high-performance multi-protocol repeater/redriver designed to support eight channels of PCIe, SAS, and other high-speed interface serial protocols up to 12.5 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of up to +30 dB at 6.25 GHz (12.5 Gbps) in each of its eight channels and is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as 30in+ backplane traces or 8m+ copper cables, hence enabling host controllers to ensure an error free end-to-end link. The strong linear equalization maximizes interconnect channel extension when the DS125BR800A is placed with the majority of channel loss on the devices input side. Adjustable transmit de-emphasis and output voltage amplitude help to compensate for the remaining channel attenuation on the output side.
When operating in SAS-3 and PCIe Gen-3 mode, the DS125BR800A transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency. With a low power consumption of 65 mW/channel (typ) and option to turn-off unused channels, the DS125BR800A enables energy efficient system design. A single supply of 3.3 V or 2.5 V is required to power the device.
The programmable settings can be applied easily via pins, software (SMBus or I2C) or loaded via an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver. |
DS125BR82012-Gbps 8-channel linear redriver with equalization | Integrated Circuits (ICs) | 2 | Active | The DS125BR820 is an extremely low-power high-performance repeater/redriver designed to support eight channels carrying high speed interface up to 12.5 Gbps, such as 40G-CR4, 40G-KR4, SAS/SATA, and PCIe. The receiver’s continuous time linear equalizer (CTLE) provides high frequency boost that is programmable from 3 to 10 dB at 6 GHz (12 Gbps) followed by a linear output driver. The CTLE receiver is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as board traces or twin axial-copper cables. The programmable equalization maximizes the flexibility of physical placement within the interconnect channel and improves overall channel performance.
When operating in 40G-CR4/KR4, SAS/SATA, and PCIe applications, the DS125BR820 preserves transmit signal characteristics, thereby allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency in the link training protocol facilitates system level interoperability and minimizes latency.
The programmable settings can be applied easily via pin control, software (SMBus or I2C), or direct loading from an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, thereby eliminating the need for an external microprocessor or software driver.
The DS125BR820 is an extremely low-power high-performance repeater/redriver designed to support eight channels carrying high speed interface up to 12.5 Gbps, such as 40G-CR4, 40G-KR4, SAS/SATA, and PCIe. The receiver’s continuous time linear equalizer (CTLE) provides high frequency boost that is programmable from 3 to 10 dB at 6 GHz (12 Gbps) followed by a linear output driver. The CTLE receiver is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as board traces or twin axial-copper cables. The programmable equalization maximizes the flexibility of physical placement within the interconnect channel and improves overall channel performance.
When operating in 40G-CR4/KR4, SAS/SATA, and PCIe applications, the DS125BR820 preserves transmit signal characteristics, thereby allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency in the link training protocol facilitates system level interoperability and minimizes latency.
The programmable settings can be applied easily via pin control, software (SMBus or I2C), or direct loading from an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, thereby eliminating the need for an external microprocessor or software driver. |
DS125DF1119.8 - 12.5-Gbps low power multi-rate two channel retimer | Interface | 2 | Active | The DS125DF111 is a dual channel (1-lane bidirectional) retimer with integrated signal conditioning. The DS125DF111 includes an input Continuous-Time Linear Equalizer (CTLE), clock and data recovery (CDR) and transmit driver on each channel.
The DS125DF111 with its on-chip Decision Feedback Equalizer (DFE) can enhance the reach and robustness of long, lossy, cross-talk-impaired high speed serial links to achieve BER < 1x10–15. For less demanding applications/interconnects, the DFE can be switched off and achieve the same BER performance. The DS125DF111 and DS110DF111 devices are pin-compatible.
Each channel of the DS125DF111 independently locks to specific serial data at data rates from 9.8 to 12.5 Gbps or to any supported sub-rate of these data rates. This simplifies system design and lowers overall cost.
Programmable transmit de-emphasis driver offers precise settings to meet the SFF-8431 output eye template. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnect and backplanes with multiple connectors. The CDR function is ideal for use in front port parallel optical module applications to reset the jitter budget and retime high speed serial data.
The DS125DF111 is a dual channel (1-lane bidirectional) retimer with integrated signal conditioning. The DS125DF111 includes an input Continuous-Time Linear Equalizer (CTLE), clock and data recovery (CDR) and transmit driver on each channel.
The DS125DF111 with its on-chip Decision Feedback Equalizer (DFE) can enhance the reach and robustness of long, lossy, cross-talk-impaired high speed serial links to achieve BER < 1x10–15. For less demanding applications/interconnects, the DFE can be switched off and achieve the same BER performance. The DS125DF111 and DS110DF111 devices are pin-compatible.
Each channel of the DS125DF111 independently locks to specific serial data at data rates from 9.8 to 12.5 Gbps or to any supported sub-rate of these data rates. This simplifies system design and lowers overall cost.
Programmable transmit de-emphasis driver offers precise settings to meet the SFF-8431 output eye template. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnect and backplanes with multiple connectors. The CDR function is ideal for use in front port parallel optical module applications to reset the jitter budget and retime high speed serial data. |
| Interface | 2 | Active | The DS125DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning features. The device includes a fully adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.
Each channel of the DS125DF1610 independently locks to serial data at 9.8 to 12.5 Gbps and the divide by 2, 4 and 8 sub-multiples. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream is used as a reference clock. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS125DF1610.
Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.
A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.
The DS125DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning features. The device includes a fully adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.
Each channel of the DS125DF1610 independently locks to serial data at 9.8 to 12.5 Gbps and the divide by 2, 4 and 8 sub-multiples. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream is used as a reference clock. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS125DF1610.
Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.
A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests. |
DS125DF4109.8 to 12.5-Gbps quad channel retimer with adaptive EQ, CDR and DFE | Specialized | 1 | Active | The DS125DF410 is four channel retimer with integrated signal conditioning. The device includes a fully adaptive Continuous-Time Linear Equalizer (CTLE), self calibrating 5-tap Decision Feedback Equalizer (DFE), Clock and Data Recovery (CDR), and transmit De-Emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1×10-15.
Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associated sub rates (div by 2, 4 and 8) to support a variety of communication protocols. A 25 MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.
The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.
The DS125DF410 is four channel retimer with integrated signal conditioning. The device includes a fully adaptive Continuous-Time Linear Equalizer (CTLE), self calibrating 5-tap Decision Feedback Equalizer (DFE), Clock and Data Recovery (CDR), and transmit De-Emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1×10-15.
Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associated sub rates (div by 2, 4 and 8) to support a variety of communication protocols. A 25 MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.
The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning. |
