Texas Instruments

The DS125MB203 device is a dual port 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning suitable for 10GE, 10G-KR (802.3ap), Fibre Channel, PCIe, Infiniband, SATA3/SAS2 and other high-speed bus applications with data rates up to 12.5 Gbps. The continuous time linear equalizer (CTLE) of the receiver provides necessary boost to compensate up to 30-inch FR-4 or 8-m cable (AWG-24) at 12.5 Gbps. This on-chip feature eliminates the need for external signal conditioners. The transmitter features a programmable amplitude voltage levels to be selectable from 600 mVp-p to 1300 mVp-p and de-emphasis of up to 12 dB. The DS125MB203 can be configured to support PCIe, SAS/SATA, 10G-KR or other signaling protocols. When operating in 10G-KR and PCIe Gen-3 mode, the DS125MB203 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency. The programmable settings can be applied through pin settings, SMBus (I2C) protocol or loaded directly from an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver. The DS125MB203 device is a dual port 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning suitable for 10GE, 10G-KR (802.3ap), Fibre Channel, PCIe, Infiniband, SATA3/SAS2 and other high-speed bus applications with data rates up to 12.5 Gbps. The continuous time linear equalizer (CTLE) of the receiver provides necessary boost to compensate up to 30-inch FR-4 or 8-m cable (AWG-24) at 12.5 Gbps. This on-chip feature eliminates the need for external signal conditioners. The transmitter features a programmable amplitude voltage levels to be selectable from 600 mVp-p to 1300 mVp-p and de-emphasis of up to 12 dB. The DS125MB203 can be configured to support PCIe, SAS/SATA, 10G-KR or other signaling protocols. When operating in 10G-KR and PCIe Gen-3 mode, the DS125MB203 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency. The programmable settings can be applied through pin settings, SMBus (I2C) protocol or loaded directly from an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.

The DS125RT410 is a four-channel retimer with integrated signal conditioning. The device includes a fully adaptive continuous-time linear equalizer (CTLE), clock and data recovery (CDR), and a transmit de-emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1 × 10–15. For channels with a high amount of crosstalk, the DS125DF410 should be used because it has self calibrating 5-tap decision-feedback equalizer (DFE). Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associated subrates (divide by 2, 4, and 8) to support a variety of communication protocols. A 25-MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data. The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded through an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning. The DS125RT410 is a four-channel retimer with integrated signal conditioning. The device includes a fully adaptive continuous-time linear equalizer (CTLE), clock and data recovery (CDR), and a transmit de-emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1 × 10–15. For channels with a high amount of crosstalk, the DS125DF410 should be used because it has self calibrating 5-tap decision-feedback equalizer (DFE). Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associated subrates (divide by 2, 4, and 8) to support a variety of communication protocols. A 25-MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data. The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded through an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.