Texas Instruments

The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174.

The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively. Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter. If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively. Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter. If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.

High Speed CMOS Logic Non-Inverting Octal-Bus Transceiver with 3-State Outputs

High Speed CMOS Logic 8-Input Multiplexer with 3-State Outputs

The ’HC257 and ’HCT257 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select Input (S). The Output Enable input (OE\) is active LOW. When OE\ is HIGH, all of the outputs (1Y-4Y) are in the high impedance state regardless of all other input conditions. Moving data from two groups of registers to four common output buses is a common use of the 257. The state of the Select input determines the particular register from which the data comes. It can also be used as a function generator. The ’HC257 and ’HCT257 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select Input (S). The Output Enable input (OE\) is active LOW. When OE\ is HIGH, all of the outputs (1Y-4Y) are in the high impedance state regardless of all other input conditions. Moving data from two groups of registers to four common output buses is a common use of the 257. The state of the Select input determines the particular register from which the data comes. It can also be used as a function generator.

High Speed CMOS Logic 8-Bit Addressable Latch

High Speed CMOS Logic Octal D-Type Flip-Flops with Reset

High Speed CMOS Logic Octal Transparent Latches with 3-State Output

High Speed CMOS Logic Dual 4-Stage Binary Counter

High Speed CMOS Logic 14-Stage Binary Counter