CD54HC4538High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator | Logic | 2 | Active | The ’HC4538 and ’HCT4538 are dual retriggerable/resettable monostable precision multivibrators for fixed voltage timing applications. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. The propagation delay from trigger input-to-output transition and the propagation delay from reset input-to-output transition are independent of RXand CX.
Leading-edge triggering (A) and trailing edge triggering (B)\ inputs are provided for triggering from either edge of the input pulse. An unused "A" input should be tied to GND and an unused B\ should be tied to VCC. On power up the IC is reset. Unused resets and sections must be terminated. In normal operation the circuit retriggers on the application of each new trigger pulse. To operate in the non-triggerable mode Q\ is connected to B\ when leading edge triggering (A) is used or Q is connected to A when trailing edge triggering (B)\ is used. The period (. CMINis 0pF.
The ’HC4538 and ’HCT4538 are dual retriggerable/resettable monostable precision multivibrators for fixed voltage timing applications. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. The propagation delay from trigger input-to-output transition and the propagation delay from reset input-to-output transition are independent of RXand CX.
Leading-edge triggering (A) and trailing edge triggering (B)\ inputs are provided for triggering from either edge of the input pulse. An unused "A" input should be tied to GND and an unused B\ should be tied to VCC. On power up the IC is reset. Unused resets and sections must be terminated. In normal operation the circuit retriggers on the application of each new trigger pulse. To operate in the non-triggerable mode Q\ is connected to B\ when leading edge triggering (A) is used or Q is connected to A when trailing edge triggering (B)\ is used. The period (. CMINis 0pF. |
CD54HC533High Speed CMOS Logic Octal InvertingTransparent Latch with 3-State Outputs | Logic | 1 | Active | The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power con-sumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch enable (LE\) is high. When the latch enable (LE\) goes low the data is latched. The output enable (OE\) controls the three-state outputs. When the output enable (OE\) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable.
The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts. The ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; the latter are non-inverting types.
The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power con-sumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch enable (LE\) is high. When the latch enable (LE\) goes low the data is latched. The output enable (OE\) controls the three-state outputs. When the output enable (OE\) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable.
The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts. The ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; the latter are non-inverting types. |
CD54HC563High Speed CMOS Logic Octal Inverting Transparent Latch with 3-State Outputs | Integrated Circuits (ICs) | 1 | Active | The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power con-sumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch enable (LE\) is high. When the latch enable (LE\) goes low the data is latched. The output enable (OE\) controls the three-state outputs. When the output enable (OE\) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable.
The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts. The ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; the latter are non-inverting types.
The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power con-sumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch enable (LE\) is high. When the latch enable (LE\) goes low the data is latched. The output enable (OE\) controls the three-state outputs. When the output enable (OE\) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable.
The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts. The ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; the latter are non-inverting types. |
CD54HC573High Speed CMOS Logic Octal Transparent Latch with 3-State Output | Logic | 1 | Active | High Speed CMOS Logic Octal Transparent Latch with 3-State Output |
CD54HC574High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State Outputs | Logic | 1 | Active | High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State Outputs |
CD54HC597High Speed CMOS Logic 8-Bit Shift Register with Input Storage | Shift Registers | 1 | Active | The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high. |
CD54HC646High Speed CMOS Logic Octal Inverting Bus Transceiver with 3-State Outputs | Integrated Circuits (ICs) | 1 | Active | The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.
Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.
Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
CD54HC7266Military 4-ch, 2-input, 2-V to 6-V 5.2 mA drive strength XNOR (exclusive NOR) gate | Gates and Inverters | 1 | Active | This device contains four independent 2-input XNOR gates. Each gate performs the Boolean function Y =A ⊕ Bin positive logic.
This device contains four independent 2-input XNOR gates. Each gate performs the Boolean function Y =A ⊕ Bin positive logic. |
CD54HC73High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset | Flip Flops | 2 | Active | High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset |
CD54HC74High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset | Flip Flops | 2 | Active | The CDx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each.
The CDx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each. |
