CD54HC597 Series

High Speed CMOS Logic 8-Bit Shift Register with Input Storage

Catalog

High Speed CMOS Logic 8-Bit Shift Register with Input Storage

Part	Function	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case	Package / Case	Number of Elements	Number of Bits per Element	Logic Type	Supplier Device Package	Output Type	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments CD54HC597F3A	Parallel or Serial to Serial	2 V	6 V	0.3 in 7.62 mm	16-CDIP	1	8	Shift Register	16-CDIP	Non-Inverted	Through Hole	125 °C	-55 °C

Catalog

High Speed CMOS Logic 8-Bit Shift Register with Input Storage

Key Features

• Buffered InputsAsynchronous Parallel LoadFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range... –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOHData sheet acquired from Harris SemiconductorBuffered InputsAsynchronous Parallel LoadFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range... –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOHData sheet acquired from Harris Semiconductor

Description

The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high. The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.