Texas Instruments

The TPS68470 device is an advanced power management unit that powers a Compact Camera Module (CCM), generates the clock for the image sensor, drives a dual LED for Flash and incorporates two LED drivers for general purpose indicators . The TPS68470 is capable of generating all needed power rails in a CCM. The CORE voltage regulator is a state of the art buck converter which can be used for the image sensor digital supply. An LDO (LDO_ANA) can be used for the image sensor analog supply. The TPS68470 also has a high efficiency boost converter to support two 1A LED flash drivers. The LED currents are controlled with regulated low side current sources. The TPS68470 has five other LDOs. Two of them can be used for generic and sensor IO supply voltage generation (LDO_IO and LDO_S_IO). One can be dedicated to the VCM driver supply (LDO_VCM). The remaining two are auxiliary LDOs (LDO_AUX1 and LDO_AUX2). The TPS68470 device is an advanced power management unit that powers a Compact Camera Module (CCM), generates the clock for the image sensor, drives a dual LED for Flash and incorporates two LED drivers for general purpose indicators . The TPS68470 is capable of generating all needed power rails in a CCM. The CORE voltage regulator is a state of the art buck converter which can be used for the image sensor digital supply. An LDO (LDO_ANA) can be used for the image sensor analog supply. The TPS68470 also has a high efficiency boost converter to support two 1A LED flash drivers. The LED currents are controlled with regulated low side current sources. The TPS68470 has five other LDOs. Two of them can be used for generic and sensor IO supply voltage generation (LDO_IO and LDO_S_IO). One can be dedicated to the VCM driver supply (LDO_VCM). The remaining two are auxiliary LDOs (LDO_AUX1 and LDO_AUX2).

TPS701xx family devices are designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution. The TPS701xx family of voltage regulators offer very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors. These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1µA at TJ= +25°C. The device is enabled when theENpin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (for example, an overload condition), VOUT1is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pull-up current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1. The TPS701xx features aRESET(SVS, POR, or Power-On Reset).RESEToutput initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition.RESETindicates the status of VOUT2and both manual reset pins (MR1andMR2). When VOUT2reaches 95% of its regulated voltage andMR1andMR2are in the logic high state,RESETgoes to a high impedance state after a 120ms delay.RESETgoes to the logic low state when the VOUT2regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected toMR1orMR2. The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1reaches 2.5V. TPS701xx family devices are designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution. The TPS701xx family of voltage regulators offer very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors. These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1µA at TJ= +25°C. The device is enabled when theENpin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (for example, an overload condition), VOUT1is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pull-up current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1. The TPS701xx features aRESET(SVS, POR, or Power-On Reset).RESEToutput initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition.RESETindicates the status of VOUT2and both manual reset pins (MR1andMR2). When VOUT2reaches 95% of its regulated voltage andMR1andMR2are in the logic high state,RESETgoes to a high impedance state after a 120ms delay.RESETgoes to the logic low state when the VOUT2regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected toMR1orMR2. The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1reaches 2.5V.

The TPS70175 is designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS70175 ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution. The TPS70175 voltage regulator offers low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors. This device has a fixed 5 V/2.5 V voltage option. Regulator 1 can support up to 500 mA and regulator 2 can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 280 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1 µA at TJ= 25°C. The device is enabled when theENpin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (for example, an overload condition), VOUT1is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1. The TPS70175 features aRESET(SVS, POR, or Power-On Reset).RESEToutput initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition.RESETindicates the status of VOUT2and both manual reset pins (MR1andMR2). When VOUT2reaches 95% of its regulated voltage andMR1andMR2are in the logic high state,RESETgoes to a high impedance state after a 30-ms delay.RESETgoes to the logic low state when the VOUT2regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected toMR1orMR2. The device has an undervoltage lockout (UVLO) circuit which prevents the internal regulators from turning on until VIN1reaches 2.5 V. The TPS70175 is designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS70175 ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution. The TPS70175 voltage regulator offers low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors. This device has a fixed 5 V/2.5 V voltage option. Regulator 1 can support up to 500 mA and regulator 2 can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 280 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1 µA at TJ= 25°C. The device is enabled when theENpin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (for example, an overload condition), VOUT1is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1. The TPS70175 features aRESET(SVS, POR, or Power-On Reset).RESEToutput initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition.RESETindicates the status of VOUT2and both manual reset pins (MR1andMR2). When VOUT2reaches 95% of its regulated voltage andMR1andMR2are in the logic high state,RESETgoes to a high impedance state after a 30-ms delay.RESETgoes to the logic low state when the VOUT2regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected toMR1orMR2. The device has an undervoltage lockout (UVLO) circuit which prevents the internal regulators from turning on until VIN1reaches 2.5 V.

The TPS702xx is a low dropout voltage regulator with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 500mA and 250mA by regulator 1 and regulator 2 respectively. Quiescent current is typically 190µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. The TPS702xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors. These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal toEN1orEN2(enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to bothEN1andEN2, both regulators enter sleep mode, thereby reducing the input current to 2µA at TJ= +25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS702xx features aRESET(SVS, POR, or power on reset).RESEToutput initiates a reset in the event of an undervoltage condition.RESETalso indicates the status of the manual reset pin (MR). WhenMRis in the logic high state,RESETgoes to a high impedance state after a 120ms delay. To monitor VOUT1, the PG1 output pin can be connected toMR. To monitor VOUT2, the PG2 output pin can be connected toMR. The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until VIN1reaches 2.5V. The TPS702xx is a low dropout voltage regulator with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 500mA and 250mA by regulator 1 and regulator 2 respectively. Quiescent current is typically 190µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. The TPS702xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors. These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal toEN1orEN2(enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to bothEN1andEN2, both regulators enter sleep mode, thereby reducing the input current to 2µA at TJ= +25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS702xx features aRESET(SVS, POR, or power on reset).RESEToutput initiates a reset in the event of an undervoltage condition.RESETalso indicates the status of the manual reset pin (MR). WhenMRis in the logic high state,RESETgoes to a high impedance state after a 120ms delay. To monitor VOUT1, the PG1 output pin can be connected toMR. To monitor VOUT2, the PG2 output pin can be connected toMR. The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until VIN1reaches 2.5V.

The TPS70345 is designed to provide a complete power management solution for Texas Instruments DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any Texas Instruments DSP applications with power sequencing requirement. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset inputs, and enable function, provide a complete system solution. The TPS70345 voltage regulator offers low dropout voltage and dual outputs with power up sequence control, which is designed primarily for DSP applications. This device has a low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47 µF low ESR capacitors. This device has a fixed output voltage 3.3 V/1.2 V. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and independent of output loading (maximum of 250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN\ (enable) shuts down both regulators, reducing the input current to 1 µA at TJ= 25°C. The device is enabled when the EN\ pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (i.e. overload condition) of its regulated voltage, VOUT1will be turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1. The PG1 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 1. The TPS70345 features a RESET (SVS, POR, or power on reset). RESET\ is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up, RESET\ goes to a high impedance state (i.e. logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1must be above the undervoltage condition. Second, the manual reset (MR)\ pin must be in a high impedance state. Third, VOUT2must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1\ or MR2\. RESET\ can be used to drive power on reset or a low-battery indicator. If RESET\ is not used, it can be left floating. Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V. The TPS70345 is designed to provide a complete power management solution for Texas Instruments DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any Texas Instruments DSP applications with power sequencing requirement. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset inputs, and enable function, provide a complete system solution. The TPS70345 voltage regulator offers low dropout voltage and dual outputs with power up sequence control, which is designed primarily for DSP applications. This device has a low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47 µF low ESR capacitors. This device has a fixed output voltage 3.3 V/1.2 V. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and independent of output loading (maximum of 250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN\ (enable) shuts down both regulators, reducing the input current to 1 µA at TJ= 25°C. The device is enabled when the EN\ pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (i.e. overload condition) of its regulated voltage, VOUT1will be turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1. The PG1 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 1. The TPS70345 features a RESET (SVS, POR, or power on reset). RESET\ is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up, RESET\ goes to a high impedance state (i.e. logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1must be above the undervoltage condition. Second, the manual reset (MR)\ pin must be in a high impedance state. Third, VOUT2must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1\ or MR2\. RESET\ can be used to drive power on reset or a low-battery indicator. If RESET\ is not used, it can be left floating. Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.

The TPS703xx family of devices is designed to provide a complete power management solution for TI DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any TI DSP application with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power-on reset), manual reset inputs, and enable function, provide a complete system solution. The TPS703xx family of voltage regulators offers very low dropout voltage and dual outputs with power up sequence control, designed primarily for DSP applications. These devices have low noise output performance without using any added filter bypass capacitors, and are designed to have a fast transient response and be stable with 47 µF low ESR capacitors. These devices have fixed 3.3 V/2.5 V, 3.3 V/1.8 V, 3.3 V/1.5 V, 3.3 V/1.2 V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1 µA at TJ= +25°C. The device is enabled when theENpin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (that is, in an overload condition) of its regulated voltage, VOUT1is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pull-up current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement an SVS (POR, or power-on reset) for the circuitry supplied by regulator 1. The TPS703xx features aRESET(SVS, POR, or power-on reset).RESETis an active low, open drain output and requires a pull-up resistor for normal operation. When pulled up,RESETgoes to a high impedance state (that is, logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third, VOUT2must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected toMR1orMR2.RESETcan be used to drive power-on reset or a low-battery indicator. IfRESETis not used, it can be left floating. Internal bias voltages are powered by VIN1and require 2.7V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V. The TPS703xx family of devices is designed to provide a complete power management solution for TI DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any TI DSP application with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power-on reset), manual reset inputs, and enable function, provide a complete system solution. The TPS703xx family of voltage regulators offers very low dropout voltage and dual outputs with power up sequence control, designed primarily for DSP applications. These devices have low noise output performance without using any added filter bypass capacitors, and are designed to have a fast transient response and be stable with 47 µF low ESR capacitors. These devices have fixed 3.3 V/2.5 V, 3.3 V/1.8 V, 3.3 V/1.5 V, 3.3 V/1.2 V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal toEN(enable) shuts down both regulators, reducing the input current to 1 µA at TJ= +25°C. The device is enabled when theENpin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1and VSENSE2pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2turns on first and VOUT1remains off until VOUT2reaches approximately 83% of its regulated output voltage. At that time VOUT1is turned on. If VOUT2is pulled below 83% (that is, in an overload condition) of its regulated voltage, VOUT1is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1is turned on first. The SEQ pin is connected to an internal pull-up current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement an SVS (POR, or power-on reset) for the circuitry supplied by regulator 1. The TPS703xx features aRESET(SVS, POR, or power-on reset).RESETis an active low, open drain output and requires a pull-up resistor for normal operation. When pulled up,RESETgoes to a high impedance state (that is, logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third, VOUT2must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected toMR1orMR2.RESETcan be used to drive power-on reset or a low-battery indicator. IfRESETis not used, it can be left floating. Internal bias voltages are powered by VIN1and require 2.7V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.

The TPS704xx family of devices consists of dual-output, low-dropout voltage regulators with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 1 A and 2 A by regulator 1 and regulator 2 respectively. Quiescent current is typically 185 µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. The TPS704xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47-µF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal toEN1orEN2(enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to bothEN1andEN2, both regulators enter sleep mode, thereby reducing the input current to 2 µA at TJ= +25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS704xx features aRESET(SVS, POR, or power on reset).RESETis an active low, open drain output and requires a pull-up resistor for normal operation. When pulled up,RESETgoes into a high impedance state (that is, logic high) after a 120-ms delay when both of the following conditions are met. First, VIN1must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor VOUT1, the PG1 output pin can be connected toMR. To monitor VOUT2, the PG2 output pin can be connected toMR.RESETcan be used to drive power on reset or a low-battery indicator. IfRESETis not used, it can be left floating. Internal bias voltages are powered by VIN1and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V. The TPS704xx family of devices consists of dual-output, low-dropout voltage regulators with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 1 A and 2 A by regulator 1 and regulator 2 respectively. Quiescent current is typically 185 µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. The TPS704xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47-µF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal toEN1orEN2(enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to bothEN1andEN2, both regulators enter sleep mode, thereby reducing the input current to 2 µA at TJ= +25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS704xx features aRESET(SVS, POR, or power on reset).RESETis an active low, open drain output and requires a pull-up resistor for normal operation. When pulled up,RESETgoes into a high impedance state (that is, logic high) after a 120-ms delay when both of the following conditions are met. First, VIN1must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor VOUT1, the PG1 output pin can be connected toMR. To monitor VOUT2, the PG2 output pin can be connected toMR.RESETcan be used to drive power on reset or a low-battery indicator. IfRESETis not used, it can be left floating. Internal bias voltages are powered by VIN1and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.