| Integrated Circuits (ICs) | 2 | Obsolete | |
74AS874Dual 4-Bit D-Type Edge-Triggered Flip-Flops | Integrated Circuits (ICs) | 3 | Active | These dual 4-bit D-type edge-triggered flip-flops feature 3-state outputs designed specifically as bus drivers. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The edge-triggered flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN54ALS874B, SN74ALS874B, and SN74AS874 have clear () inputs and noninverting Q outputs. The SN74ALS876A and SN74AS876 have preset () inputs and inverting Q\ outputs; takinglow causes the four Q or Q\ outputs to go low independently of the clock.
The SN54ALS874B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS874B, SN74ALS876A, SN74AS874, and SN74AS876 devices are characterized for operation from 0°C to 70°C.
These dual 4-bit D-type edge-triggered flip-flops feature 3-state outputs designed specifically as bus drivers. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The edge-triggered flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN54ALS874B, SN74ALS874B, and SN74AS874 have clear () inputs and noninverting Q outputs. The SN74ALS876A and SN74AS876 have preset () inputs and inverting Q\ outputs; takinglow causes the four Q or Q\ outputs to go low independently of the clock.
The SN54ALS874B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS874B, SN74ALS876A, SN74AS874, and SN74AS876 devices are characterized for operation from 0°C to 70°C. |
| Logic | 2 | Obsolete | |
| Integrated Circuits (ICs) | 1 | Active | |
| Integrated Circuits (ICs) | 4 | Active | These advanced Schottky devices are capable of performing high-speed arithmetic or logic comparisons on two 8-bit binary or two's complement words. Two fully decoded decisions about words P and Q are externally available at two outputs. These devices are fully expandable to any number of bits without external gates. To compare words of longer lengths, the P > QOUT and P < QOUT outputs of a stage handling less significant bits can be connected to the P > QIN and P < QIN inputs of the next stage handling more significant bits. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. Two alternative methods of cascading are shown in application information.
The latch is transparent when P latch-enable (PLE) input is high; the P-input port is latched
when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE, P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically -0.25 mA, which minimizes dc loading effects.
The SN54AS885 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS885 is characterized for operation from 0°C to 70°C.
In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.
AG = arithmetically greater than
These advanced Schottky devices are capable of performing high-speed arithmetic or logic comparisons on two 8-bit binary or two's complement words. Two fully decoded decisions about words P and Q are externally available at two outputs. These devices are fully expandable to any number of bits without external gates. To compare words of longer lengths, the P > QOUT and P < QOUT outputs of a stage handling less significant bits can be connected to the P > QIN and P < QIN inputs of the next stage handling more significant bits. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. Two alternative methods of cascading are shown in application information.
The latch is transparent when P latch-enable (PLE) input is high; the P-input port is latched
when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE, P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically -0.25 mA, which minimizes dc loading effects.
The SN54AS885 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS885 is characterized for operation from 0°C to 70°C.
In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.
AG = arithmetically greater than |
| Shift Registers | 1 | Active | |
| Gates and Inverters | 2 | Active | |
74AUC066-ch, 0.8-V to 2.7-V high speed inverters with open-drain outputs | Gates and Inverters | 1 | Active | This hex inverter buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation.
The outputs of the SN74AUC06 are open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This hex inverter buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation.
The outputs of the SN74AUC06 are open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
| Integrated Circuits (ICs) | 2 | Active | |
74AUC1254-ch, 0.8-V to 2.7-V high speed buffers with 3-state outputs | Logic | 2 | Active | This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCCoperation, but is designed specifically for 1.6-V to 1.95-V VCCoperation.
The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCCoperation, but is designed specifically for 1.6-V to 1.95-V VCCoperation.
The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
