Texas Instruments

The ADS58H43 is a high-linearity, quad-channel, 14-bit, 250-MSPS analog-to-digital converter (ADC). The four ADC channels are separated into two blocks with two ADCs each. Each block can be individually configured into three different operating modes. One operating mode includes the implementation of the SNRBoost3G+signal processing technology to provide high signal-to-noise ratio (SNR) in a band up to 90 MHz wide with only 11-bit resolution. Designed for low power consumption and high spurious-free dynamic range (SFDR), the ADC has low-noise performance and outstanding SFDR over a large input frequency range. The ADS58H43 is a high-linearity, quad-channel, 14-bit, 250-MSPS analog-to-digital converter (ADC). The four ADC channels are separated into two blocks with two ADCs each. Each block can be individually configured into three different operating modes. One operating mode includes the implementation of the SNRBoost3G+signal processing technology to provide high signal-to-noise ratio (SNR) in a band up to 90 MHz wide with only 11-bit resolution. Designed for low power consumption and high spurious-free dynamic range (SFDR), the ADC has low-noise performance and outstanding SFDR over a large input frequency range.

The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD observation receiver. The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel. The ADS58J63 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS58J63 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth. The ADS58J63 also supports a 14-bit, 500-MSPS output in burst-mode making the device suitable for a DPD observation receiver. The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.

The ADS58J64 is a low-power, wide-bandwidth, 14-bit, 1-GSPS, quad-channel, telecom receiver device. The ADS58J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS58J64 also supports a 14-bit, 500-MSPS output in burst mode, making the device suitable for a digital pre-distortion (DPD) observation receiver. The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADS58J64 is a low-power, wide-bandwidth, 14-bit, 1-GSPS, quad-channel, telecom receiver device. The ADS58J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS58J64 also supports a 14-bit, 500-MSPS output in burst mode, making the device suitable for a digital pre-distortion (DPD) observation receiver. The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems. Key Specifications: The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems. Key Specifications:

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies. It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges. The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability. The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up. ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported. The devices are specified over the industrial temperature range (-40°C to 85°C). ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies. It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges. The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability. The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up. ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported. The devices are specified over the industrial temperature range (-40°C to 85°C).