Texas Instruments

The ADS556x is a high-performance 16-bit family of ADCs with sampling rates up to 80 MSPS. The device supports very-high SNR for input frequencies in the first Nyquist zone. The device includes a low-frequency noise suppression mode that improves the noise from DC to about 1 MHz. In addition to high performance, the device offers several flexible features such as output interface (either Double Data Rate [DDR] LVDS or parallel CMOS) and fine gain in 1-dB steps until 6-dB maximum gain. Innovative techniques, such as DDR LVDS and an internal reference that does not require external decoupling capacitors, have been used to achieve significant savings in pin count. This innovation results in a compact 7-mm × 7-mm 48-pin VQFN package. The device can be put in an external reference mode, where the VCM pin behaves as the external reference input. For applications where power is important, the ADS556x device offers power down modes and automatic power scaling at lower sample rates. The device is specified over the industrial temperature range of –40°C to 85°C. The ADS556x is a high-performance 16-bit family of ADCs with sampling rates up to 80 MSPS. The device supports very-high SNR for input frequencies in the first Nyquist zone. The device includes a low-frequency noise suppression mode that improves the noise from DC to about 1 MHz. In addition to high performance, the device offers several flexible features such as output interface (either Double Data Rate [DDR] LVDS or parallel CMOS) and fine gain in 1-dB steps until 6-dB maximum gain. Innovative techniques, such as DDR LVDS and an internal reference that does not require external decoupling capacitors, have been used to achieve significant savings in pin count. This innovation results in a compact 7-mm × 7-mm 48-pin VQFN package. The device can be put in an external reference mode, where the VCM pin behaves as the external reference input. For applications where power is important, the ADS556x device offers power down modes and automatic power scaling at lower sample rates. The device is specified over the industrial temperature range of –40°C to 85°C.

The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2). Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination. The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C). The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2). Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination. The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).

The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2). Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination. The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C). The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2). Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination. The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).

The ADS58C20 and ADS58C23 are dual IF receivers for wideband, multi-mode cellular infrastructure base stations. Each channel provides high dynamic performance up to 125 MHz of bandwidth, with optimized bands of 40- and 75-MHz. The IF receiver architecture eases front end filter design for wide bandwidth receivers. The receivers have integrated buffers at the analog inputs with benefits of uniform performance and input impedance across a wide frequency range. The ADS58C20 is a high performance part with superior specifications for single/multi-mode cellular base-station receivers that include multi-carrier GSM. It can also process other cellular protocols such as TDS-CDMA/3G/LTE and prior generation systems. The ADS58C23 offers the same functionality and pinout as ADS58C20 but with reduced minimum performance specifications for lower cost and performance systems, such as TDS-CDMA/3G/LTE single/multi-mode receivers (when GSM is not required). It can also process prior generation protocols. The devices are available in a 80-pin TQFP package, and are specified over the full industrial temperature range (–40°C to 85°C). The ADS58C20 and ADS58C23 are dual IF receivers for wideband, multi-mode cellular infrastructure base stations. Each channel provides high dynamic performance up to 125 MHz of bandwidth, with optimized bands of 40- and 75-MHz. The IF receiver architecture eases front end filter design for wide bandwidth receivers. The receivers have integrated buffers at the analog inputs with benefits of uniform performance and input impedance across a wide frequency range. The ADS58C20 is a high performance part with superior specifications for single/multi-mode cellular base-station receivers that include multi-carrier GSM. It can also process other cellular protocols such as TDS-CDMA/3G/LTE and prior generation systems. The ADS58C23 offers the same functionality and pinout as ADS58C20 but with reduced minimum performance specifications for lower cost and performance systems, such as TDS-CDMA/3G/LTE single/multi-mode receivers (when GSM is not required). It can also process prior generation protocols. The devices are available in a 80-pin TQFP package, and are specified over the full industrial temperature range (–40°C to 85°C).

The ADS58C20 and ADS58C23 are dual IF receivers for wideband, multi-mode cellular infrastructure base stations. Each channel provides high dynamic performance up to 125 MHz of bandwidth, with optimized bands of 40- and 75-MHz. The IF receiver architecture eases front end filter design for wide bandwidth receivers. The receivers have integrated buffers at the analog inputs with benefits of uniform performance and input impedance across a wide frequency range. The ADS58C20 is a high performance part with superior specifications for single/multi-mode cellular base-station receivers that include multi-carrier GSM. It can also process other cellular protocols such as TDS-CDMA/3G/LTE and prior generation systems. The ADS58C23 offers the same functionality and pinout as ADS58C20 but with reduced minimum performance specifications for lower cost and performance systems, such as TDS-CDMA/3G/LTE single/multi-mode receivers (when GSM is not required). It can also process prior generation protocols. The devices are available in a 80-pin TQFP package, and are specified over the full industrial temperature range (–40°C to 85°C). The ADS58C20 and ADS58C23 are dual IF receivers for wideband, multi-mode cellular infrastructure base stations. Each channel provides high dynamic performance up to 125 MHz of bandwidth, with optimized bands of 40- and 75-MHz. The IF receiver architecture eases front end filter design for wide bandwidth receivers. The receivers have integrated buffers at the analog inputs with benefits of uniform performance and input impedance across a wide frequency range. The ADS58C20 is a high performance part with superior specifications for single/multi-mode cellular base-station receivers that include multi-carrier GSM. It can also process other cellular protocols such as TDS-CDMA/3G/LTE and prior generation systems. The ADS58C23 offers the same functionality and pinout as ADS58C20 but with reduced minimum performance specifications for lower cost and performance systems, such as TDS-CDMA/3G/LTE single/multi-mode receivers (when GSM is not required). It can also process prior generation protocols. The devices are available in a 80-pin TQFP package, and are specified over the full industrial temperature range (–40°C to 85°C).

The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications. The ADS58C48 uses third-generationSNRBoost3Gtechnology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in theSNRBoost3Gtechnology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separateSNRBoost3Gcoefficients can be programmed for each channel. The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50termination (such as the two clock ports of the GC5330). The same digital output pins can also be configured as a parallel 1.8V CMOS interface. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C). The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications. The ADS58C48 uses third-generationSNRBoost3Gtechnology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in theSNRBoost3Gtechnology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separateSNRBoost3Gcoefficients can be programmed for each channel. The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50termination (such as the two clock ports of the GC5330). The same digital output pins can also be configured as a parallel 1.8V CMOS interface. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).

The ADS58H40 is a high-linearity, quad-channel, 14-bit, 250-MSPS analog-to-digital converter (ADC). The four ADC channels are separated into two blocks with two ADCs each. Each block can be individually configured into three different operating modes. One operating mode includes the implementation of the SNRBoost3G+signal processing technology to provide high signal-to-noise ratio (SNR) in a band up to 90 MHz wide with only 11-bit resolution. Designed for low power consumption and high spurious-free dynamic range (SFDR), the ADC has low-noise performance and outstanding SFDR over a large input frequency range. The ADS58H40 is a high-linearity, quad-channel, 14-bit, 250-MSPS analog-to-digital converter (ADC). The four ADC channels are separated into two blocks with two ADCs each. Each block can be individually configured into three different operating modes. One operating mode includes the implementation of the SNRBoost3G+signal processing technology to provide high signal-to-noise ratio (SNR) in a band up to 90 MHz wide with only 11-bit resolution. Designed for low power consumption and high spurious-free dynamic range (SFDR), the ADC has low-noise performance and outstanding SFDR over a large input frequency range.