74AS298Quadruple 2-Input Multiplexers With Storage | Integrated Circuits (ICs) | 5 | Active | The SN74AS298A is a quadruple 2-input multiplexer with storage that provides essentially the equivalent functional capabilities of two separate MSI functions (SN74AS157 and ´AS175A) in a 16-pin package.
When the word-select (WS) input is low, word 1 (A1, B1, C1, D1) is applied to the flip-flops. A high input to WS causes the selection of word 2 (A2, B2, C2, D2). The selected word is clocked to the output terminals on the negative-going edge of the clock pulse.
The SN74AS298A is characterized for operation from 0°C to 70°C.
a1, a2, etc. = the level of steady-state input at A1, A2, etc.QA0, QB0, etc. = the level of QA, QB, etc. entered on the most recent transition of CLK
The SN74AS298A is a quadruple 2-input multiplexer with storage that provides essentially the equivalent functional capabilities of two separate MSI functions (SN74AS157 and ´AS175A) in a 16-pin package.
When the word-select (WS) input is low, word 1 (A1, B1, C1, D1) is applied to the flip-flops. A high input to WS causes the selection of word 2 (A2, B2, C2, D2). The selected word is clocked to the output terminals on the negative-going edge of the clock pulse.
The SN74AS298A is characterized for operation from 0°C to 70°C.
a1, a2, etc. = the level of steady-state input at A1, A2, etc.QA0, QB0, etc. = the level of QA, QB, etc. entered on the most recent transition of CLK |
| Logic | 5 | Active | |
| Logic | 5 | Active | |
74AS373Octal D-Type Transparent Latches with 3-state Outputs | Integrated Circuits (ICs) | 5 | Active | These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. |
74AS374Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs | Integrated Circuits (ICs) | 6 | Active | These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C.
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C. |
| Latches | 3 | Active | |
| Flip Flops | 2 | Active | |
74AS573Octal D-Type Transparent Latches With 3-State Outputs | Latches | 3 | Active | These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, outputs (Q) respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.
A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
does not affect internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C.
These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, outputs (Q) respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.
A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
does not affect internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C. |
74AS574Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs | Flip Flops | 3 | Active | These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN74ALS575A, SN54AS575, and SN74AS575 may be synchronously cleared by taking the clear () input low.
The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS574B, SN54AS574, and SN54AS575 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS574B, SN74ALS575A, SN74AS574, and SN74AS575 are characterized for operation from 0°C to 70°C.
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN74ALS575A, SN54AS575, and SN74AS575 may be synchronously cleared by taking the clear () input low.
The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS574B, SN54AS574, and SN54AS575 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS574B, SN74ALS575A, SN74AS574, and SN74AS575 are characterized for operation from 0°C to 70°C. |
| Logic | 1 | Active | |
