ADS58C48 Series

Quad-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC)

Catalog

Quad-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC)

Part	Package / Case	Sampling Rate (Per Second)	Voltage - Supply [Max]	Voltage - Supply [Min]	Data Interface	Operating Temperature [Max]	Operating Temperature [Min]	Resolution (Bits)	Mounting Type	Supplier Device Package	Voltage Supply Source	Type	Number of Channels	Number of A/D Converters	Input Range	Number of Bits	Supplied Contents	Utilized IC / Part
Texas Instruments ADS58C48IPFPR	80-TQFP Exposed Pad	200 M	1.9 V	1.7 V	Parallel Serial	85 °C	-40 °C	11 b	Surface Mount	80-HTQFP (12x12)	Analog and Digital	ADC	4
Texas Instruments ADS58C48EVM		200 M			Parallel Serial									4	2 Vpp	11	Board(s)	ADS58C48
Texas Instruments ADS58C48IPFP	80-TQFP Exposed Pad	200 M	1.9 V	1.7 V	Parallel Serial	85 °C	-40 °C	11 b	Surface Mount	80-HTQFP (12x12)	Analog and Digital	ADC	4

Catalog

Quad-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC)

Key Features

• Maximum Sample Rate: 200 MSPSHigh Dynamic PerformanceSFDR 82 dBc at 140 MHz72.3 dBFS SNR in 60 MHz BW UsingSNRBoost3GtechnologySNRBoost3GHighlightsSupports Wide Bandwidth up to 60 MHzProgrammable Bandwidths – 60 MHz, 40 MHz, 30 MHz, 20 MHzFlat Noise Floor within the BandIndependentSNRBoost3GCoefficients for Every ChannelOutput InterfaceDouble Data Rate (DDR) LVDS with Programmable Swing and StrengthStandard Swing: 350mVLow Swing: 200mVDefault Strength: 100Termination2x Strength: 50Termination1.8V Parallel CMOS Interface Also SupportedUltra-Low Power with Single 1.8V Supply0.9W Total Power1.32 W Total Power (200 MSPS) withSNRBoost3Gon all 4 Channels1.12 W Total Power (200 MSPS) withSNRBoost3Gon 2 ChannelsProgrammable Gain up to 6dB for SNR/SFDR Trade-OffDC Offset CorrectionSupports Low Input Clock Amplitude80-TQFP PackageMaximum Sample Rate: 200 MSPSHigh Dynamic PerformanceSFDR 82 dBc at 140 MHz72.3 dBFS SNR in 60 MHz BW UsingSNRBoost3GtechnologySNRBoost3GHighlightsSupports Wide Bandwidth up to 60 MHzProgrammable Bandwidths – 60 MHz, 40 MHz, 30 MHz, 20 MHzFlat Noise Floor within the BandIndependentSNRBoost3GCoefficients for Every ChannelOutput InterfaceDouble Data Rate (DDR) LVDS with Programmable Swing and StrengthStandard Swing: 350mVLow Swing: 200mVDefault Strength: 100Termination2x Strength: 50Termination1.8V Parallel CMOS Interface Also SupportedUltra-Low Power with Single 1.8V Supply0.9W Total Power1.32 W Total Power (200 MSPS) withSNRBoost3Gon all 4 Channels1.12 W Total Power (200 MSPS) withSNRBoost3Gon 2 ChannelsProgrammable Gain up to 6dB for SNR/SFDR Trade-OffDC Offset CorrectionSupports Low Input Clock Amplitude80-TQFP Package

Description

The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications. The ADS58C48 uses third-generationSNRBoost3Gtechnology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in theSNRBoost3Gtechnology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separateSNRBoost3Gcoefficients can be programmed for each channel. The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50termination (such as the two clock ports of the GC5330). The same digital output pins can also be configured as a parallel 1.8V CMOS interface. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C). The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications. The ADS58C48 uses third-generationSNRBoost3Gtechnology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in theSNRBoost3Gtechnology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separateSNRBoost3Gcoefficients can be programmed for each channel. The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50termination (such as the two clock ports of the GC5330). The same digital output pins can also be configured as a parallel 1.8V CMOS interface. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).