Texas Instruments

The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel. The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.

The ADS5463/ADS54RF63 is a 12-bit, 500-/550-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs. This ADC is one of a family of 12-, 13-, and 14-bit ADCs that operate from 210 MSPS to 550 MSPS. The ADS5463/ADS54RF63 input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. The ADS54RF63 provides superior SFDR compared to the ADS5463 when the analog input frequency exceeds ~350 MHz or if operation up to 550 MSPS is required. The ADS5463/ADS54RF63 is available in a TQFP-80 PowerPAD™ package. The ADS5463/ADS54RF63 is built on the Texas Instrument complementary bipolar process (BiCom3) and specified over the full industrial temperature range (-40°C to 85°C). The ADS5463/ADS54RF63 is a 12-bit, 500-/550-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs. This ADC is one of a family of 12-, 13-, and 14-bit ADCs that operate from 210 MSPS to 550 MSPS. The ADS5463/ADS54RF63 input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. The ADS54RF63 provides superior SFDR compared to the ADS5463 when the analog input frequency exceeds ~350 MHz or if operation up to 550 MSPS is required. The ADS5463/ADS54RF63 is available in a TQFP-80 PowerPAD™ package. The ADS5463/ADS54RF63 is built on the Texas Instrument complementary bipolar process (BiCom3) and specified over the full industrial temperature range (-40°C to 85°C).

The ADS54T01 is a high linearity, single channel, 12-bit, 750-Msps analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data—the data can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high-resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196-pin NFBGA package and is specified over the full industrial temperature range (–40°C to 85°C). The ADS54T01 is a high linearity, single channel, 12-bit, 750-Msps analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data—the data can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high-resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196-pin NFBGA package and is specified over the full industrial temperature range (–40°C to 85°C).

The ADS54T02 is a high linearity dual channel 12-bit, 750 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data – it can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C). The ADS54T02 is a high linearity dual channel 12-bit, 750 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data – it can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

The ADS54T04 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data – it can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C). The ADS54T04 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data – it can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

The ADS5500-EP is a high-performance, 14-bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in a small space, the ADS5500-EP has excellent power consumption of 780 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. A parallel CMOS-compatible output ensures seamless interfacing with common logic. The ADS5500-EP is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of –55°C to +125°C. The ADS5500-EP is a high-performance, 14-bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in a small space, the ADS5500-EP has excellent power consumption of 780 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. A parallel CMOS-compatible output ensures seamless interfacing with common logic. The ADS5500-EP is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of –55°C to +125°C.

The ADS5510 is a high-performance, 11 bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in little space, the ADS5510 has excellent power consumption of 578 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS-compatible output ensures seamless interfacing with common logic. The ADS5510 is available in 64-pin TQFP PowerPAD™ package over the industrial temperature range. The ADS5510 is a high-performance, 11 bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in little space, the ADS5510 has excellent power consumption of 578 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS-compatible output ensures seamless interfacing with common logic. The ADS5510 is available in 64-pin TQFP PowerPAD™ package over the industrial temperature range.

The ADS5520 is a high-performance, 12-Bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in little space, the ADS5520 has excellent power consumption of 578 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS-compatible output ensures seamless interfacing with common logic. The ADS5520 is available in a 64-pin TQFP PowerPAD package over the industrial temperature range. The ADS5520 is a high-performance, 12-Bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in little space, the ADS5520 has excellent power consumption of 578 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS-compatible output ensures seamless interfacing with common logic. The ADS5520 is available in a 64-pin TQFP PowerPAD package over the industrial temperature range.