Texas Instruments

These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation: Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low. The SN54AS194 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C. These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation: Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low. The SN54AS194 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C.

These devices contain two independent 4-input positive-AND gates. They perform the Boolean functionsorin positive logic. The SN54ALS21A and SN54AS21 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS21A and SN74AS21 are characterized for operation from 0°C to 70°C. These devices contain two independent 4-input positive-AND gates. They perform the Boolean functionsorin positive logic. The SN54ALS21A and SN54AS21 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS21A and SN74AS21 are characterized for operation from 0°C to 70°C.

These octal buffers/drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. When these devices are used with the ’ALS241, ’AS241A, ’ALS244, and ’AS244A devices, the circuit designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs. These devices feature high fan-out and improved fan-in. The -1 version of SN74ALS240A is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS240A. These octal buffers/drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. When these devices are used with the ’ALS241, ’AS241A, ’ALS244, and ’AS244A devices, the circuit designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs. These devices feature high fan-out and improved fan-in. The -1 version of SN74ALS240A is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS240A.

These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the ´ALS240A, ´ALS241C, ´AS240A, and ´AS241A, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. The -1 version of SN74ALS244C is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS244C. The SN54ALS244C and SN54AS244A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS244C and SN74AS244A are characterized for operation from 0°C to 70°C. These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the ´ALS240A, ´ALS241C, ´AS240A, and ´AS241A, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. The -1 version of SN74ALS244C is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS244C. The SN54ALS244C and SN54AS244A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS244C and SN74AS244A are characterized for operation from 0°C to 70°C.

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated. The -1 version of the SN74ALS245A is identical to the standard version, except that the recommended maximum IOLis increased to 48 mA. There is no -1 version of the SN54ALS245A. These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated. The -1 version of the SN74ALS245A is identical to the standard version, except that the recommended maximum IOLis increased to 48 mA. There is no -1 version of the SN54ALS245A.