SN74AS286 Series

9-Bit Parity Generators/Checkers With Bus-Driver Parity I/O Ports

Catalog

9-Bit Parity Generators/Checkers With Bus-Driver Parity I/O Ports

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Operating Temperature [Max]	Package / Case	Package / Case [y]	Package / Case [x]	Number of Circuits	Logic Type	Supplier Device Package
Texas Instruments SN74AS286N	15 mA	48 mA	20 mA	2 mA	4.5 V	5.5 V	Through Hole	70 °C	14-DIP	7.62 mm	0.3 "	9-Bit	Parity Generator/Checker
Texas Instruments SN74AS286NSR	15 mA	48 mA	20 mA	2 mA	4.5 V	5.5 V	Surface Mount	70 °C	14-SOIC	5.3 mm	0.209 "	9-Bit	Parity Generator/Checker	14-SO
Texas Instruments SN74AS286D	15 mA	48 mA	20 mA	2 mA	4.5 V	5.5 V	Surface Mount	70 °C	14-SOIC	3.9 mm	0.154 in	9-Bit	Parity Generator/Checker

Catalog

9-Bit Parity Generators/Checkers With Bus-Driver Parity I/O Ports

Key Features

• Generate Either Odd or Even Parity forNine Data LinesCascadable for n-Bit ParityDirect Bus Connection for Parity Generation or Checking by Using the Parity I/O PortGlitch-Free Bus During Power Up/DownPackage Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPsGenerate Either Odd or Even Parity forNine Data LinesCascadable for n-Bit ParityDirect Bus Connection for Parity Generation or Checking by Using the Parity I/O PortGlitch-Free Bus During Power Up/DownPackage Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

Description

The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-drivingparity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading. The transmit () control input is implemented specifically to accommodate cascading. Whenis low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. Whenis high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level. The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches. The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C. The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-drivingparity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading. The transmit () control input is implemented specifically to accommodate cascading. Whenis low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. Whenis high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level. The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches. The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C.