Texas Instruments

The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with the benefits of constant performance and input impedance across a wide frequency range. The device is well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The device supports both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500MBPS) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The device has a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination. The device is available in a compact QFN-48 package and is specified over the industrial temperature range (–40°C to +85°C). The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with the benefits of constant performance and input impedance across a wide frequency range. The device is well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The device supports both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500MBPS) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The device has a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination. The device is available in a compact QFN-48 package and is specified over the industrial temperature range (–40°C to +85°C).

The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination. The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C). The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination. The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination. The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C). The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination. The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

The ADS424x and ADS422x family of devices are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit or 12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8-V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications. The ADS424x and ADS422x family of devices are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit or 12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8-V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4229 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4229 well-suited for multi-carrier, wide-bandwidth communications applications. The ADS4229 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available in a compact QFN-64 PowerPAD™ package. The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4229 is specified over the industrial temperature range (–40°C to +85°C). The ADS4229 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4229 well-suited for multi-carrier, wide-bandwidth communications applications. The ADS4229 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available in a compact QFN-64 PowerPAD™ package. The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4229 is specified over the industrial temperature range (–40°C to +85°C).

The ADS424x and ADS422x family of devices are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit or 12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8-V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications. The ADS424x and ADS422x family of devices are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit or 12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8-V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4245 is a low-speed variant of the ADS42xx ultralow-power family of dual-channel, 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8V supply. This topology makes the ADS4245 well-suited for multi-carrier, wide-bandwidth communications applications. The ADS4245 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. These device includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR (double data rate) LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 PowerPAD™ package. The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4245 is specified over the military temperature range (–55°C to 125°C). The ADS4245 is a low-speed variant of the ADS42xx ultralow-power family of dual-channel, 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8V supply. This topology makes the ADS4245 well-suited for multi-carrier, wide-bandwidth communications applications. The ADS4245 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. These device includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR (double data rate) LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 PowerPAD™ package. The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4245 is specified over the military temperature range (–55°C to 125°C).