Texas Instruments

The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications. The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package. The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C). The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications. The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package. The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).

The ADS42JB46 is a high-linearity, dual-channel, 14-bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range. The ADS42JB46 is a high-linearity, dual-channel, 14-bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range. The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range. The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.