Texas Instruments

These devices contain four independent 2-input AND gates. The open-collector outputs require pull-up resistors to perform correctly. They may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOHlevels. The SN5409, SN54LS09, and SN54S09 are characterized for operation over the full military temperature range of -55°C to 125°C, The SN7409, SN74LS09, and SN74S09 are characterized for operation from 0°C to 70°C. These devices contain four independent 2-input AND gates. The open-collector outputs require pull-up resistors to perform correctly. They may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOHlevels. The SN5409, SN54LS09, and SN54S09 are characterized for operation over the full military temperature range of -55°C to 125°C, The SN7409, SN74LS09, and SN74S09 are characterized for operation from 0°C to 70°C.

These devices contain three independent 3-input NAND gates. The SN5410, SN54LS10, and SN54S10 are characterized for operation over the full military temperature range of –55°C to 125°C. The SN7410, SN74LS10 and SN74S10 are characterized for operation from 0°C to 70°C. These devices contain three independent 3-input NAND gates. The SN5410, SN54LS10, and SN54S10 are characterized for operation over the full military temperature range of –55°C to 125°C. The SN7410, SN74LS10 and SN74S10 are characterized for operation from 0°C to 70°C.

This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of a 12-bit high-speed Schottky diode array suitable for clamping to VCCand/or GND. This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of a 12-bit high-speed Schottky diode array suitable for clamping to VCCand/or GND.

This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of a 16-bit high-speed Schottky diode array suitable for clamping to VCCand/or GND. The SN74S1053 is characterized for operation from 0°C to 70°C. This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of a 16-bit high-speed Schottky diode array suitable for clamping to VCCand/or GND. The SN74S1053 is characterized for operation from 0°C to 70°C.

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C. These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.

The 'S124 features two independent voltage-controlled oscillators (VCO) in a single monolithic chip. The output frequency of each VCO is established by an external capacitor in combination with two voltage-sensitive inputs, one for frequency range and one for frequency control. These inputs can be used to vary the output frequency as shown under typical characteristics. These highly stable oscillators can be set to operate at any frequency typically between 0.12 hertz and 85 megahertz. While the enable input is low, the output is enabled. While the enable input is high, the output is high. These devices can operate from a single 5-volt supply. However, one set of supply-voltage and ground pins (VCCand GND) is provided for the enable, synchronization-gating, and output sections, and a separate set (GND) and is provided for the oscillator and associated frequency-control circuits so that effective isolation can be accomplished in the system. The enable input of these devices starts or stops the output pulses when it is low or high, respectively. The internal oscillator of the 'S124 is started and stopped by the enable input. The enable input is one standard load; it and the buffered output operate at standard Schottky-clamped TTL levels. The pulse synchronization-gating section ensures that the first output pulse is neither clipped nor extended. Duty cycle of the square-wave output is fixed at approximately 50 percent. The SN54S124 is characterized for operation over the full military temperature range of –55°C to 125°C; the SN74S124 is characterized for operation from 0°C to 70°C. The 'S124 features two independent voltage-controlled oscillators (VCO) in a single monolithic chip. The output frequency of each VCO is established by an external capacitor in combination with two voltage-sensitive inputs, one for frequency range and one for frequency control. These inputs can be used to vary the output frequency as shown under typical characteristics. These highly stable oscillators can be set to operate at any frequency typically between 0.12 hertz and 85 megahertz. While the enable input is low, the output is enabled. While the enable input is high, the output is high. These devices can operate from a single 5-volt supply. However, one set of supply-voltage and ground pins (VCCand GND) is provided for the enable, synchronization-gating, and output sections, and a separate set (GND) and is provided for the oscillator and associated frequency-control circuits so that effective isolation can be accomplished in the system. The enable input of these devices starts or stops the output pulses when it is low or high, respectively. The internal oscillator of the 'S124 is started and stopped by the enable input. The enable input is one standard load; it and the buffered output operate at standard Schottky-clamped TTL levels. The pulse synchronization-gating section ensures that the first output pulse is neither clipped nor extended. Duty cycle of the square-wave output is fixed at approximately 50 percent. The SN54S124 is characterized for operation over the full military temperature range of –55°C to 125°C; the SN74S124 is characterized for operation from 0°C to 70°C.

These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The 'LS138, SN54S138, and SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. All of these decoder/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design. The SN54LS138 and SN54S138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS138 and SN74S138A are characterized for operation from 0°C to 70°C. These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The 'LS138, SN54S138, and SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. All of these decoder/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design. The SN54LS138 and SN54S138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS138 and SN74S138A are characterized for operation from 0°C to 70°C.

These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast-enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The circuit comprises two individual two-line to four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design. The SN54LS139A and SN54S139 are characterized for operation range of –55°C to 125°C. The SN74LS139A and SN74S139A are characterized for operation from 0°C to 70°C. These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast-enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The circuit comprises two individual two-line to four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design. The SN54LS139A and SN54S139 are characterized for operation range of –55°C to 125°C. The SN74LS139A and SN74S139A are characterized for operation from 0°C to 70°C.

These devices contain two independent 4-input positive-NAND 50-ohm line drivers. They perform the Boolean function Y = ABCD\. The SN54S140 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74S140 is characterized for operation from 0°C to 70°C. These devices contain two independent 4-input positive-NAND 50-ohm line drivers. They perform the Boolean function Y = ABCD\. The SN54S140 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74S140 is characterized for operation from 0°C to 70°C.