| Integrated Circuits (ICs) | 3 | Active | This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCH16952A contains two sets of D-type flip-flops for temporary storage of data flowing in either direction. The device can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CEAB\ or CEBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCH16952A contains two sets of D-type flip-flops for temporary storage of data flowing in either direction. The device can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CEAB\ or CEBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. |
SN74LVCH16T245-EPEnhanced Product 16-Bit Dual-Supply Bus Transc., Configurable Voltage Translation, 3-State Outputs | Logic | 9 | Active | This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCAaccepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCBaccepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVCH16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.
The SN74LVCH16T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICCand ICCZ.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCCisolation feature ensures that if either VCCinput is at GND, then all outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCAaccepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCBaccepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVCH16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.
The SN74LVCH16T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICCand ICCZ.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCCisolation feature ensures that if either VCCinput is at GND, then all outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
SN74LVCH244A8-ch, 1.65-V to 3.6-V buffers with bus-hold and 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 9 | Active | The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V VCCoperation.
These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. WhenOEis low, these devices pass data from the A inputs to the Y outputs. WhenOEis high, the outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V VCCoperation.
These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. WhenOEis low, these devices pass data from the A inputs to the Y outputs. WhenOEis high, the outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Logic | 16 | Active | The SN54LVCH245A octal bus transceiver is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVCH245A octal bus transceiver is designed for 1.65-V to 3.6-V VCCoperation. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
The SN54LVCH245A octal bus transceiver is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVCH245A octal bus transceiver is designed for 1.65-V to 3.6-V VCCoperation. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. |
SN74LVCH8T2458-bit dual-supply bus transceiver with configurable voltage translation and 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 6 | Active | The SN74LVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.
The SN74LVCH8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs, the A-port outputs, or place both output ports into a high-impedance state. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device. The VCCisolation feature ensures that if either VCCAor VCCBis at GND, then the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCAthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVCH8T245 is designed so that the control pins (DIR andOE) are referenced to VCCA.
The SN74LVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.
The SN74LVCH8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs, the A-port outputs, or place both output ports into a high-impedance state. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device. The VCCisolation feature ensures that if either VCCAor VCCBis at GND, then the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCAthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVCH8T245 is designed so that the control pins (DIR andOE) are referenced to VCCA. |
| Integrated Circuits (ICs) | 7 | Active | This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCHR16245A device is designed for asynchronous communication between data buses. The control-function implementation minimizes external-timing requirements.
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCHR16245A device is designed for asynchronous communication between data buses. The control-function implementation minimizes external-timing requirements. |
| Logic | 3 | Active | This 16-bit (dual-octal) noninverting bus transceiver is designed for 2.7-V to 3.6-V VCCoperation.
The SN74LVCR162245 is designed forasynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated.
All outputs, which are designed to sink up to 12 mA, include 26-resistors to reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE\ or DIR.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 16-bit (dual-octal) noninverting bus transceiver is designed for 2.7-V to 3.6-V VCCoperation.
The SN74LVCR162245 is designed forasynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated.
All outputs, which are designed to sink up to 12 mA, include 26-resistors to reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE\ or DIR.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Buffers, Drivers, Receivers, Transceivers | 3 | Active | This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCR16245A device is designed for asynchronous communication between data buses. All inputs and outputs have equivalent 26-Ω resistors that will slow the edges of the output and reduce switching noise caused by long capacitive etch runs or cables.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state.
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCR16245A device is designed for asynchronous communication between data buses. All inputs and outputs have equivalent 26-Ω resistors that will slow the edges of the output and reduce switching noise caused by long capacitive etch runs or cables.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. |
| Integrated Circuits (ICs) | 12 | Active | The SN74LVCR2245A device is an octal bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCR2245A device is an octal bus transceiver is designed for 1.65-V to 3.6-V VCCoperation. |
| Logic | 10 | Active | This hex inverter is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCU04A contains six independent inverters with unbuffered outputs and performs the Boolean function Y = A\.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
This hex inverter is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVCU04A contains six independent inverters with unbuffered outputs and performs the Boolean function Y = A\.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. |
