Catalog
Three-line to eight-line decoders/demultiplexers
Key Features
• Inputs Are TTL-Voltage Compatible4.5-V to 5.5-V VCCOperationMax tpdof 7.6 ns at 5 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 5 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>>2.3 V at VCC= 5 V, TA= 25°CSupport Mixed-Mode Voltage Operation on All PortsIoffSupports Partial-Power Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Inputs Are TTL-Voltage Compatible4.5-V to 5.5-V VCCOperationMax tpdof 7.6 ns at 5 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 5 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>>2.3 V at VCC= 5 V, TA= 25°CSupport Mixed-Mode Voltage Operation on All PortsIoffSupports Partial-Power Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)
Description
AI
The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1,G2A,G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
This device is fully specified for partial-power-down application susing Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1,G2A,G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
This device is fully specified for partial-power-down application susing Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
