Texas Instruments

The SN74HCS153-Q1 is a dual data selector/multiplexer containing full binary decoding to select one of four data sources. Both channels are controlled by the same address select inputs, and each channel includes its own strobe (G) input. A high level at the strobe terminal forces the respective output low. The SN74HCS153-Q1 is a dual data selector/multiplexer containing full binary decoding to select one of four data sources. Both channels are controlled by the same address select inputs, and each channel includes its own strobe (G) input. A high level at the strobe terminal forces the respective output low.

The SN74HCS157-Q1 contains four data selectors/multiplexers to select one of two data sources. All channels are controlled by the same address select (A/B) input, and strobe (G) input. A high level at the strobe terminal forces all outputs low. The SN74HCS157-Q1 contains four data selectors/multiplexers to select one of two data sources. All channels are controlled by the same address select (A/B) input, and strobe (G) input. A high level at the strobe terminal forces all outputs low.

The SN74HCS164-Q1 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The SN74HCS164-Q1 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals.

The SN74HCS165-Q1 is a parallel- or serial-in, serial-out 8-bit shift register with Schmitt-trigger inputs. The SN74HCS165-Q1 is a parallel- or serial-in, serial-out 8-bit shift register with Schmitt-trigger inputs.

The SN74HCS16507 is a parallel- or serial-in, serial-out 8-bit shift register with open-drain outputs and Schmitt-trigger inputs. The SN74HCS16507 is a parallel- or serial-in, serial-out 8-bit shift register with open-drain outputs and Schmitt-trigger inputs.

The SN74HCS166 device contains an 8-bit shift register with one serial input and eight parallel-load inputs. The SN74HCS166 device contains an 8-bit shift register with one serial input and eight parallel-load inputs.

The SN74HCS174-Q1 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR) inputs. The SN74HCS174-Q1 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR) inputs.

This device contains two independent 4-input NAND gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A ● B ● C ● Din positive logic. This device contains two independent 4-input NAND gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A ● B ● C ● Din positive logic.

This device contains two independent 4-input AND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B ● C ● D in positive logic. This device contains two independent 4-input AND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B ● C ● D in positive logic.

The SN74HCS237-Q1 is a three to eight decoder with latched address inputs, one standard output strobe (G0), and one active low output strobe (G1). When the latch enable (LE) input is low, the device acts as a standard three to eight decoder. When the latch enable (LE) input is high, the address latch retains its previous state. When the outputs are gated by either strobe input, they are all forced into the low state. When the outputs are not disabled by one or both of the strobe inputs, only the selected output is high while all others are low. The SN74HCS237-Q1 is a three to eight decoder with latched address inputs, one standard output strobe (G0), and one active low output strobe (G1). When the latch enable (LE) input is low, the device acts as a standard three to eight decoder. When the latch enable (LE) input is high, the address latch retains its previous state. When the outputs are gated by either strobe input, they are all forced into the low state. When the outputs are not disabled by one or both of the strobe inputs, only the selected output is high while all others are low.