| Logic | 9 | Active | This hex inverter contains six independent inverters designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC04 performs the Boolean function Y = A\.
This hex inverter contains six independent inverters designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC04 performs the Boolean function Y = A\. |
SN74ALVC08-Q1Enhanced product, 4-ch, 2-input 1.65-V to 3.6-V ultra-high-speed (3 ns) AND gate | Gates and Inverters | 16 | Active | The SN74ALVC08 quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCCoperation.
The device performs the Boolean function Y = A • B or Y (A\ + B\)\ in positive logic.
The SN74ALVC08 quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCCoperation.
The device performs the Boolean function Y = A • B or Y (A\ + B\)\ in positive logic. |
SN74ALVC103-ch, 3-input, 1.65-V to 3.6-V NAND gates | Gates and Inverters | 6 | Active | This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC10 performs the Boolean function Y = (A • B • C)\ or Y = A\ + B\ + C\ in positive logic.
This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC10 performs the Boolean function Y = (A • B • C)\ or Y = A\ + B\ + C\ in positive logic. |
SN74ALVC1254-ch, 1.65-V to 3.6-V buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 9 | Active | This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
SN74ALVC1264-ch, 1.65-V to 3.6-V buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 4 | Active | This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. |
SN74ALVC146-ch, 2.3-V to 3.6-V inverters with Schmitt-Trigger inputs | Integrated Circuits (ICs) | 7 | Active | This hex Schmitt-trigger inverter is designed for 2.3-V to 3.6-V VCCoperation.
The SN74ALVC14 contains six independent inverters and performs the Boolean function Y = A\.
This hex Schmitt-trigger inverter is designed for 2.3-V to 3.6-V VCCoperation.
The SN74ALVC14 contains six independent inverters and performs the Boolean function Y = A\. |
| Logic | 3 | Active | This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Logic | 4 | Active | This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC16244A is designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVC16244A is designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Integrated Circuits (ICs) | 3 | Active | This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The output port includes equivalent 26-series resistors to reduce overshoot and undershoot.
This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The output port includes equivalent 26-series resistors to reduce overshoot and undershoot. |
| Universal Bus Functions | 2 | Active | This 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The output port includes equivalent 26-series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The output port includes equivalent 26-series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
