Texas Instruments

The SNx4AHC574 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The SNx4AHC574 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The SNx4AHC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided on the shift and storage registers. A serial (QH′) output is provided for cascading purposes. The SNx4AHC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided on the shift and storage registers. A serial (QH′) output is provided for cascading purposes.

The SN74AHC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state. The SN74AHC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state.

The SN74AHC74 dual positive-edge-triggered device is a D-type flip-flop. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN74AHC74 dual positive-edge-triggered device is a D-type flip-flop. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The ’AHCT00 device performs the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic. The ’AHCT00 device performs the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic.

Enhanced product, 4-ch 2-input 4.5-V to 5.5-V AND gate with TTL-compatible inputs