Texas Instruments

The SN74AHC1G14 device is a single inverter gate. The device performs the Boolean function Y = A. The SN74AHC1G14 device is a single inverter gate. The device performs the Boolean function Y = A.

Automotive, one-channel two-input 2V to 5.5V high-speed (9 ns) OR gate

The SN74AHC1G86-Q1 is a single 2-input exclusive-OR gate. The device performs the Boolean function Y = A ⊕ B or Y = AB + A B in positive logic. A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. The SN74AHC1G86-Q1 is a single 2-input exclusive-OR gate. The device performs the Boolean function Y = A ⊕ B or Y = AB + A B in positive logic. A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output.

The SN74AHC1GU04 device contains a single inverter gate. The device performs the Boolean function Y =A. The SN74AHC1GU04 device contains a single inverter gate. The device performs the Boolean function Y =A.

8-ch, 2-V to 5.5-V inverters with 3-state outputs

These octal buffers and drivers are designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. These octal buffers and drivers are designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74AHC245Q octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74AHC245Q octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.