ADC12SJ1600-Q1Single-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator | Integrated Circuits (ICs) | 4 | Active | ADC12xJ1600-Q1 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600-Q1 suited for light detection and ranging (LiDAR) systems. ADC12xJ1600-Q1 is qualified for automotive applications.
Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
ADC12xJ1600-Q1 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600-Q1 suited for light detection and ranging (LiDAR) systems. ADC12xJ1600-Q1 is qualified for automotive applications.
Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. |
ADC12SJ800Single-channel, 12-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface | Integrated Circuits (ICs) | 2 | Active | ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.
Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.
Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. |
ADC12SJ800-Q1Automotive single-channel, 12-bit, 800-MSPS ADC with JESD204C interface | Integrated Circuits (ICs) | 2 | Active | ADC12xJ800-Q1 is a family of quad, dual and single channel, 12-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC12xJ800-Q1 is qualified for automotive applications.
Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
ADC12xJ800-Q1 is a family of quad, dual and single channel, 12-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC12xJ800-Q1 is qualified for automotive applications.
Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. |
ADC12V17012-Bit, 170-MSPS, 1.1-GHz Input Bandwidth Analog-to-Digital Converter (ADC) | Integrated Circuits (ICs) | 1 | Active | The ADC12V170 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 12-Bit digital words at rates up to 170 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data Rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC12V170 operates from dual +3.3V and +1.8V power supplies and consumes 781 mW of power at 170 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.
The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC12V170 can be operated with an external reference.
Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.
The ADC12V170 is pin-compatible with the ADC14V155. It is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.
The ADC12V170 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 12-Bit digital words at rates up to 170 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data Rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC12V170 operates from dual +3.3V and +1.8V power supplies and consumes 781 mW of power at 170 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.
The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC12V170 can be operated with an external reference.
Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.
The ADC12V170 is pin-compatible with the ADC14V155. It is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C. |
| Development Boards, Kits, Programmers | 1 | Active | |
ADC1415514-Bit, 155-MSPS, 1.1-GHz Input Bandwidth Analog-to-Digital Converter (ADC) | Integrated Circuits (ICs) | 1 | Active | The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967 mW of power at 155 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation.
The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14155 can be operated with an external reference.
The ADC14155 can be configured for either single-ended or differential operation. Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC14155 is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.
The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967 mW of power at 155 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation.
The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14155 can be operated with an external reference.
The ADC14155 can be configured for either single-ended or differential operation. Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC14155 is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C. |
ADC141S62614-Bit, 50kSPS to 250kSPS, Differential Input, Micro Power ADC | Analog to Digital Converters (ADC) | 2 | Active | The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is maintained from the internal sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection. The ADC141S626 features an external reference that can be varied from 1.0V to VA. It also features a zero-power track mode where the ADC is consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied analog input voltage.
The serial data output is binary 2's complement and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. The conversion result is clocked out by the serial clock input and is the result of the conversion currently in progress; thus, ADC141S626 has no latency.
The ADC141S626 may be operated with independent analog (VA) and digital input/output (VIO) supplies. VAand VIOcan range from 2.7V to 5.5V and can be set independent of each other. This allows a user to maximize performance and minimize power consumption by operating the analog portion of the ADC at a VAof 5V while communicating with a 3V controller on the digital side. With a 3V source, the power consumption when operating at 200 kSPS is 2.0 mW. With a 5V source, the power consumption when operating at 250 kSPS is 4.8 mW. The power consumption drops down to 4 µW and 13 µW respectively when the ADC141S626 enters acquisition (power-down) mode. The differential input, low power consumption, and small size make the ADC141S626 ideal for direct connection to bridge sensors and transducers in battery operated systems or remote data acquisition applications.
Operation is guaranteed over the temperature range of −40°C to +85°C and clock rates of 0.9 MHz to 4.5 MHz. The ADC141S626 is available in a 10-lead VSSOP package.
The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is maintained from the internal sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection. The ADC141S626 features an external reference that can be varied from 1.0V to VA. It also features a zero-power track mode where the ADC is consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied analog input voltage.
The serial data output is binary 2's complement and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces. The conversion result is clocked out by the serial clock input and is the result of the conversion currently in progress; thus, ADC141S626 has no latency.
The ADC141S626 may be operated with independent analog (VA) and digital input/output (VIO) supplies. VAand VIOcan range from 2.7V to 5.5V and can be set independent of each other. This allows a user to maximize performance and minimize power consumption by operating the analog portion of the ADC at a VAof 5V while communicating with a 3V controller on the digital side. With a 3V source, the power consumption when operating at 200 kSPS is 2.0 mW. With a 5V source, the power consumption when operating at 250 kSPS is 4.8 mW. The power consumption drops down to 4 µW and 13 µW respectively when the ADC141S626 enters acquisition (power-down) mode. The differential input, low power consumption, and small size make the ADC141S626 ideal for direct connection to bridge sensors and transducers in battery operated systems or remote data acquisition applications.
Operation is guaranteed over the temperature range of −40°C to +85°C and clock rates of 0.9 MHz to 4.5 MHz. The ADC141S626 is available in a 10-lead VSSOP package. |
ADC141S628-Q1Automotive 14-Bit 200kSPS Pseudo-Differential Micro-Power Analog-to-Digital Converter (ADC) | Integrated Circuits (ICs) | 2 | Active | The ADC141S628-Q1 device is a 14-bit, 200-kSPS, pseudo-differential, analog-to-digital converter (ADC) that is AEC-Q100 grade 2 qualified. The converter is based on a successive-approximation register (SAR) architecture and has pseudo-differential analog inputs. The signal path is maintained from the internal sample-and-hold circuits throughout the ADC to provide excellent common-mode noise rejection. The ADC141S628-Q1 features a zero-power track mode where the ADC is consuming the minimum amount of supply current while the internal sampling capacitor tracks the applied analog input voltage.
The serial data output of the ADC141S628-Q1 is straight binary and is compatible with several standards, such as SPI, QSPI, Microwire, and many common DSP serial interfaces. The ADC141S628-Q1 has no latency which means the conversion result is clocked out by the serial clock input and is the result of the conversion currently in progress.
The ADC141S628-Q1 can be operated with independent analog (VA) and digital input/output (VIO) supplies. VA and VIO can range from 4.5 V to 5.5 V and can be set independent of each other. This functionality allows a user to maximize performance and minimize power consumption. Similarly, the ADC141S628-Q1 uses an external reference that can be varied from 1.0 V to VA allowing users to optimize the full dynamic range of the input. The pseudo-differential input, low power consumption, and small size make the ADC141S628-Q1 ideal for remote data acquisition applications.
Operation is specified over the temperature range of –40°C to +105°C and clock rates of 0.36 MHz to 3.6 MHz. The ADC141S628-Q1 is available in a 10-lead package.
The ADC141S628-Q1 device is a 14-bit, 200-kSPS, pseudo-differential, analog-to-digital converter (ADC) that is AEC-Q100 grade 2 qualified. The converter is based on a successive-approximation register (SAR) architecture and has pseudo-differential analog inputs. The signal path is maintained from the internal sample-and-hold circuits throughout the ADC to provide excellent common-mode noise rejection. The ADC141S628-Q1 features a zero-power track mode where the ADC is consuming the minimum amount of supply current while the internal sampling capacitor tracks the applied analog input voltage.
The serial data output of the ADC141S628-Q1 is straight binary and is compatible with several standards, such as SPI, QSPI, Microwire, and many common DSP serial interfaces. The ADC141S628-Q1 has no latency which means the conversion result is clocked out by the serial clock input and is the result of the conversion currently in progress.
The ADC141S628-Q1 can be operated with independent analog (VA) and digital input/output (VIO) supplies. VA and VIO can range from 4.5 V to 5.5 V and can be set independent of each other. This functionality allows a user to maximize performance and minimize power consumption. Similarly, the ADC141S628-Q1 uses an external reference that can be varied from 1.0 V to VA allowing users to optimize the full dynamic range of the input. The pseudo-differential input, low power consumption, and small size make the ADC141S628-Q1 ideal for remote data acquisition applications.
Operation is specified over the temperature range of –40°C to +105°C and clock rates of 0.36 MHz to 3.6 MHz. The ADC141S628-Q1 is available in a 10-lead package. |
| Evaluation Boards | 4 | Obsolete | |
ADC14C08014-Bit, 80-MSPS, 1.0-GHz Input Bandwidth Analog-to-Digital Converter (ADC) | Data Acquisition | 1 | Active | The ADC14C080 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 80 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC14C080 may be operated from a single +3.0V power supply and consumes low power.
A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14C080 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC14C080 is available in a 32-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.
The ADC14C080 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 80 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC14C080 may be operated from a single +3.0V power supply and consumes low power.
A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14C080 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC14C080 is available in a 32-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C. |
