SN74ACT8997Scan Path Linkers With 4-Bit Identification Buses Scan-Controlled TAP Concatenators | Integrated Circuits (ICs) | 2 | Active | The 'ACT8997 are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of components facilitates testing of complex circuit-board assemblies.
The 'ACT8997 enhance the scan capability of TI's SCOPETMfamily by allowing augmentation of a system's primary scan path with secondary scan paths (SSPs), which can be individually selected by the 'ACT8997 for inclusion in the primary scan path. These devices also provide buffering of test signals to reduce the need for external logic.
By loading the proper values into the instruction register and data registers, the user can select up to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any of the device's six data registers or the instruction register can be placed in the device's scan path, i.e., placed between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.
All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on either the rising or falling edge of DCI.
The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.
The SN54ACT8997 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8997 is characterized for operation from 0°C to 70°C.
The 'ACT8997 are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of components facilitates testing of complex circuit-board assemblies.
The 'ACT8997 enhance the scan capability of TI's SCOPETMfamily by allowing augmentation of a system's primary scan path with secondary scan paths (SSPs), which can be individually selected by the 'ACT8997 for inclusion in the primary scan path. These devices also provide buffering of test signals to reduce the need for external logic.
By loading the proper values into the instruction register and data registers, the user can select up to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any of the device's six data registers or the instruction register can be placed in the device's scan path, i.e., placed between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.
All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on either the rising or falling edge of DCI.
The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.
The SN54ACT8997 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8997 is characterized for operation from 0°C to 70°C. |
SN74AHC00-EPEnhanced product 4-ch, 2-input, 2-V to 5.5-V NAND gates | Integrated Circuits (ICs) | 18 | Active | The SN74AHC00 device performs the Boolean function Y = A • B or Y = A + B in positive logic.
The SN74AHC00 device performs the Boolean function Y = A • B or Y = A + B in positive logic. |
SN74AHC02-EPEnhanced product 4-ch, 2-input, 2-V to 5.5-V NOR gates | Integrated Circuits (ICs) | 15 | Active | The ’AHC02 device contains four independent 2-input NOR gates that perform the Boolean function Y = A\ • B\ or Y = (A + B)\ in positive logic.
The ’AHC02 device contains four independent 2-input NOR gates that perform the Boolean function Y = A\ • B\ or Y = (A + B)\ in positive logic. |
| Gates and Inverters | 24 | Active | The ’AHC04 devices contain six independent inverters. These devices perform the Boolean function Y = A.
The ’AHC04 devices contain six independent inverters. These devices perform the Boolean function Y = A. |
SN74AHC056-ch, 2-V to 5.5-V inverters with open-drain outputs | Logic | 4 | Active | The ’AHC05 devices contain six independent inverters. These devices perform the Boolean function Y = A\.
The open-drain outputs require pullup resistors to perform correctly. They can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
The ’AHC05 devices contain six independent inverters. These devices perform the Boolean function Y = A\.
The open-drain outputs require pullup resistors to perform correctly. They can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. |
SN74AHC08Q-Q1Enhanced product, 4-ch, 2-input 2-V to 5.5-V high-speed (9 ns) AND gate | Logic | 12 | Active | The SNx4AHC08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function Y = A • B or Y = A + B in positive logic.
The SNx4AHC08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function Y = A • B or Y = A + B in positive logic. |
SN74AHC123A-EPEnhanced Product Dual Retriggerable Monostable Multivibrator | Integrated Circuits (ICs) | 5 | Active | The SN74AHC123A device is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCCoperation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, theAinput is low, and the B input goes high. In the second method, the B input is high, and theAinput goes low. In the third method, theAinput is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cextand Rext/Cext(positive) and an external resistor connected between Rext/Cextand VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cextand VCC. The output pulse duration can be reduced by takingCLRlow.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. TheA, B, andCLRinputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by takingCLRlow.CLRcan be used to overrideAor B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.
The variance in output pulse duration from device to device is less than ±0.5% (typ) for given external timing components.
During power up, Q outputs are in the low state andQoutputs are in the high state. The outputs are glitch free, without applying a reset pulse.
For additional application information on multivibrators, see the application reportDesigning With the SN74AHC123A and SN74AHCT123A, literature number SCLA014.
The SN74AHC123A device is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCCoperation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, theAinput is low, and the B input goes high. In the second method, the B input is high, and theAinput goes low. In the third method, theAinput is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cextand Rext/Cext(positive) and an external resistor connected between Rext/Cextand VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cextand VCC. The output pulse duration can be reduced by takingCLRlow.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. TheA, B, andCLRinputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by takingCLRlow.CLRcan be used to overrideAor B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.
The variance in output pulse duration from device to device is less than ±0.5% (typ) for given external timing components.
During power up, Q outputs are in the low state andQoutputs are in the high state. The outputs are glitch free, without applying a reset pulse.
For additional application information on multivibrators, see the application reportDesigning With the SN74AHC123A and SN74AHCT123A, literature number SCLA014. |
SN74AHC125-EPEnhanced product 4-ch, 2-V to 5.5-V buffers with 3-state outputs | Integrated Circuits (ICs) | 24 | Active | The SNx4AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SNx4AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
SN74AHC1264-ch, 2-V to 5.5-V buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 8 | Active | The SNx4AHC126 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
For the high-impedance state during power up or power down, OE can be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the drive.
The SNx4AHC126 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
For the high-impedance state during power up or power down, OE can be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the drive. |
SN74AHC126-Q1Automotive four-channel 2-V to 5.5-V buffers with tri-state outputs | Buffers, Drivers, Receivers, Transceivers | 2 | Active | The SN74AHC126-Q1 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
For the high-impedance state during power up or power down, OE can be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the drive.
The SN74AHC126-Q1 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
For the high-impedance state during power up or power down, OE can be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the drive. |
