| Logic | 1 | Unknown | |
74AHC1324-ch 4-input 2-V to 5.5-V NAND gates with Schmitt-Trigger inputs | Integrated Circuits (ICs) | 6 | Active | The SN7AHC132 device is a quadruple positive-NAND gate designed for 2V to 5.5V VCC operation. This device performs the Boolean functionY = A × B or Y = A + B in positive logic.
Schmitt-trigger inputs provide added noise immunity and support for slow input signal transitions.
The SN7AHC132 device is a quadruple positive-NAND gate designed for 2V to 5.5V VCC operation. This device performs the Boolean functionY = A × B or Y = A + B in positive logic.
Schmitt-trigger inputs provide added noise immunity and support for slow input signal transitions. |
| Logic | 13 | Active | |
74AHC139Dual 2-line to 4-line demultiplexer and decoder | Integrated Circuits (ICs) | 11 | Active | The SN74AHC139 are dual 2-line to 4-line decoders/demultiplexers designed for 2V to 5.5V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The SN74AHC139 are dual 2-line to 4-line decoders/demultiplexers designed for 2V to 5.5V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. |
74AHC14Automotive 6-ch, 2-V to 5.5-V inverters with Schmitt-Trigger inputs | Gates and Inverters | 22 | Active | The SN74AHC14 contains six independent inverters. This device performs the Boolean function Y = A\.
Each circuit functions as an independent inverter, but because of the Schmitt action, the inverters have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
The SN74AHC14 contains six independent inverters. This device performs the Boolean function Y = A\.
Each circuit functions as an independent inverter, but because of the Schmitt action, the inverters have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. |
74AHC157Quadruple 2-Line To 1-Line Data Selectors / Multiplexers | Logic | 12 | Active | These quadruple 2-line to 1-line data selectors/multiplexers are designed for 2V to 5.5V VCC operation.
The SNx4AHC157 devices feature a common strobe (G) input. When the strobe is high, all outputs are low. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The devices provide true data.
These quadruple 2-line to 1-line data selectors/multiplexers are designed for 2V to 5.5V VCC operation.
The SNx4AHC157 devices feature a common strobe (G) input. When the strobe is high, all outputs are low. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The devices provide true data. |
74AHC158Quadruple 2-Line To 1-Line Data Selectors / Multiplexers | Logic | 9 | Active | These quadruple 2-line to 1-line data selectors/multiplexers are designed for 2-V to 5.5-V VCCoperation.
The ’AHC158 devices feature a common strobe (G)\ input. When the strobe is high, all outputs are high. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. These devices provide inverted data.
These quadruple 2-line to 1-line data selectors/multiplexers are designed for 2-V to 5.5-V VCCoperation.
The ’AHC158 devices feature a common strobe (G)\ input. When the strobe is high, all outputs are high. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. These devices provide inverted data. |
| Integrated Circuits (ICs) | 5 | Active | |
74AHC1624416-ch, 2-V to 5.5-V buffers with 3-state outputs | Integrated Circuits (ICs) | 5 | Active | The SNx4AHC16244 devices are 16-bit buffers and line drivers designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SNx4AHC16244 devices are 16-bit buffers and line drivers designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. |
74AHC1637316-Bit Transparent D-Type Latches With 3-State Outputs | Integrated Circuits (ICs) | 2 | Active | The 'AHC16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54AHC16373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AHC16373 is characterized for operation from -40°C to 85°C.
The 'AHC16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54AHC16373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AHC16373 is characterized for operation from -40°C to 85°C. |
