Texas Instruments

The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are single, low-voltage, differential line drivers and receivers in the small-outline transistor package. The outputs comply with the TIA/EIA-644 standard and provide a minimum differential output voltage magnitude of 247mV into a 100Ω load at signaling rates up to 630Mbps for drivers and 400Mbps for receivers. When the SN65LVDS1 device is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make the device ideal for battery-powered applications. The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are characterized for operation from –40°C to 85°C. The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are single, low-voltage, differential line drivers and receivers in the small-outline transistor package. The outputs comply with the TIA/EIA-644 standard and provide a minimum differential output voltage magnitude of 247mV into a 100Ω load at signaling rates up to 630Mbps for drivers and 400Mbps for receivers. When the SN65LVDS1 device is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make the device ideal for battery-powered applications. The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are characterized for operation from –40°C to 85°C.

The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter. The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input toENenables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100-characteristic impedance. Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open. All devices are characterized for operation from -40°C to 85°C. The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter. The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input toENenables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100-characteristic impedance. Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open. All devices are characterized for operation from -40°C to 85°C.

The SN65LVDS22 and SN65LVDM22 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The receiver outputs can be switched to either or both drivers through the multiplexer control signals S0 and S1. This allows the flexibility to perform splitter or signal routing functions with a single device. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-load. The intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics). The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40°C to 85°C. The SN65LVDS22 and SN65LVDM22 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The receiver outputs can be switched to either or both drivers through the multiplexer control signals S0 and S1. This allows the flexibility to perform splitter or signal routing functions with a single device. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-load. The intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics). The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40°C to 85°C.

The SN65LVDS250 and SN65LVDT250 are 4x4 nonblocking crosspoint switches in a flow-through pin-out allowing for ease in PCB layout. Low-voltage differential signaling (LVDS) is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT250 incorporates 110-termination resistors for those applications where board space is a premium. The SN65LVDS250 and SN65LVDT250 are characterized for operation from –40°C to 85°C. The SN65LVDS250 and SN65LVDT250 are 4x4 nonblocking crosspoint switches in a flow-through pin-out allowing for ease in PCB layout. Low-voltage differential signaling (LVDS) is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT250 incorporates 110-termination resistors for those applications where board space is a premium. The SN65LVDS250 and SN65LVDT250 are characterized for operation from –40°C to 85°C.

The SN65LVDS301 serializer device converts 27 parallel data inputs to 1, 2, or 3 Sub Low-Voltage Differential Signaling (SubLVDS) serial outputs. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30, 15, or 10 times the pixel-clock data rate depending on the number of serial links used. A copy of the pixel clock is output on a separate differential output. FPC cabling typically interconnects the SN65LVDS301 with the display. Compared to parallel signaling, the LVDS301 outputs significantly reduce the EMI of the interconnect by over 20 dB. The electromagnetic emission of the device itself is very low and meets the meets SAE J1752/3 ’M’-spec. (see Figure 6-22) The SN65LVDS301 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS inputs offer failsafe features to protect them from damage during power-up and to avoid current flow into the device inputs during power-up. An input voltage of up to 2.165 V can be applied to all CMOS inputs while VDDis between 0V and 1.65V. The SN65LVDS301 serializer device converts 27 parallel data inputs to 1, 2, or 3 Sub Low-Voltage Differential Signaling (SubLVDS) serial outputs. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30, 15, or 10 times the pixel-clock data rate depending on the number of serial links used. A copy of the pixel clock is output on a separate differential output. FPC cabling typically interconnects the SN65LVDS301 with the display. Compared to parallel signaling, the LVDS301 outputs significantly reduce the EMI of the interconnect by over 20 dB. The electromagnetic emission of the device itself is very low and meets the meets SAE J1752/3 ’M’-spec. (see Figure 6-22) The SN65LVDS301 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS inputs offer failsafe features to protect them from damage during power-up and to avoid current flow into the device inputs during power-up. An input voltage of up to 2.165 V can be applied to all CMOS inputs while VDDis between 0V and 1.65V.

The SN65LVDS31 is a differential line driver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. This driver will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled. The intended application of this device and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS31 is characterized for operation from –55°C to 125°C. The SN65LVDS31 is a differential line driver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. This driver will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled. The intended application of this device and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS31 is characterized for operation from –55°C to 125°C.

The SN65LVDS311 serializer transmits 27 parallel input data over 1, 2, or 3 serial output links. The device pinout is optimized to interface with the OMAP3630 application processor. The device loads a shift register with the 24 pixel bits and 3 control bits from the parallel CMOS input interface. The data are latched into the device by the pixel clock, PCLK. In addition to the 27 bits, the device adds a parity bit and two reserved bits for a total number of 30 serial bits. The parity bit allows a receiver to detect single-bit errors. Odd parity is implemented. The serial shift register is uploaded through 1, 2, or 3 serial outputs at 30, 15, or 10 times the pixel clock data rate. A copy of the pixel clock is output on an additional differential output. The serial data and clock are transmitted via Sub Low-Voltage Differential Signaling (SubLVDS) lines. The SN65LVDS311 supports three power modes (Shutdown, Standby and Active) to conserve power. When transmitting, the PLL locks to the incoming pixel clock PCLK and generates an internal high-speed clock at the line rate of the data lines. The parallel data is latched on the rising edge of PCLK. The serialized data is presented on the serial outputs D0, D1, D2 with a recreation of the Pixel clock PCLK generated from the internal high-speed clock and output on the CLK output. If the input clock PCLK stops, the device enters a standby mode to conserve power. Two Link-Select lines LS0 and LS1 control whether 1, 2 or 3 serial links are used. The TXEN input may be used to put the SN65LVDS311 in a shutdown mode. The SN65LVDS311 enters an active Standby mode if the input clock PCLK stops. This minimizes power consumption without the need for controlling an external pin. The SN65LVDS311 is characterized for operation over ambient air temperatures of -40°C to 85°C. All CMOS inputs offer failsafe to protect the input from damage during power-up and to avoid current flow into the device inputs during power-up. The SN65LVDS311 serializer transmits 27 parallel input data over 1, 2, or 3 serial output links. The device pinout is optimized to interface with the OMAP3630 application processor. The device loads a shift register with the 24 pixel bits and 3 control bits from the parallel CMOS input interface. The data are latched into the device by the pixel clock, PCLK. In addition to the 27 bits, the device adds a parity bit and two reserved bits for a total number of 30 serial bits. The parity bit allows a receiver to detect single-bit errors. Odd parity is implemented. The serial shift register is uploaded through 1, 2, or 3 serial outputs at 30, 15, or 10 times the pixel clock data rate. A copy of the pixel clock is output on an additional differential output. The serial data and clock are transmitted via Sub Low-Voltage Differential Signaling (SubLVDS) lines. The SN65LVDS311 supports three power modes (Shutdown, Standby and Active) to conserve power. When transmitting, the PLL locks to the incoming pixel clock PCLK and generates an internal high-speed clock at the line rate of the data lines. The parallel data is latched on the rising edge of PCLK. The serialized data is presented on the serial outputs D0, D1, D2 with a recreation of the Pixel clock PCLK generated from the internal high-speed clock and output on the CLK output. If the input clock PCLK stops, the device enters a standby mode to conserve power. Two Link-Select lines LS0 and LS1 control whether 1, 2 or 3 serial links are used. The TXEN input may be used to put the SN65LVDS311 in a shutdown mode. The SN65LVDS311 enters an active Standby mode if the input clock PCLK stops. This minimizes power consumption without the need for controlling an external pin. The SN65LVDS311 is characterized for operation over ambient air temperatures of -40°C to 85°C. All CMOS inputs offer failsafe to protect the input from damage during power-up and to avoid current flow into the device inputs during power-up.

The SN65LVDS314 receiver de-serializes FlatLink™3G compliant serial input data to 27 parallel data outputs. The SN65LVDS314 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the Channel Parity Error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle. The serial data and clock are received via Sub Low-Voltage Differential Signalling (SubLVDS) lines. The SN65LVDS314 supports three operating power modes (Shutdown, Standby, and Active) to conserve power. When receiving, the PLL locks to the incoming clock CLK and generates an internal high-speed clock at the line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The deserialized data is presented on the parallel output bus with a recreation of the Pixel clock PCLK generated from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with the PCLK and DE held low, while all other parallel outputs are pulled high. The parallel (CMOS) output bus offers a bus-swap feature. The SWAP control pin controls the output pin order of the output pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the LCD driver pinout or to put the receiver device on the top side or the bottom side of the PCB. The F/S control input selects between a slow CMOS bus output rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher load designs. Two Link Select lines LS0 and LS1 select whether 1, 2, or 3 serial links are used. The RXEN input may be used to put the SN65LVDS314 in a Shutdown mode. The SN65LVDS314 enters an active Standby mode if the common mode voltage of the CLK input becomes shifted to VDDLVDS (e.g., transmitter releases the CLK output into high-impedance). This minimizes power consumption without the need of switching an external control pin. The SN65LVDS314 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS and SubLVDS signals are 2-V tolerant with VDD= 0 V. This feature allows signal powerup before VDDis stabilized. The SN65LVDS314 receiver de-serializes FlatLink™3G compliant serial input data to 27 parallel data outputs. The SN65LVDS314 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the Channel Parity Error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle. The serial data and clock are received via Sub Low-Voltage Differential Signalling (SubLVDS) lines. The SN65LVDS314 supports three operating power modes (Shutdown, Standby, and Active) to conserve power. When receiving, the PLL locks to the incoming clock CLK and generates an internal high-speed clock at the line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The deserialized data is presented on the parallel output bus with a recreation of the Pixel clock PCLK generated from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with the PCLK and DE held low, while all other parallel outputs are pulled high. The parallel (CMOS) output bus offers a bus-swap feature. The SWAP control pin controls the output pin order of the output pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the LCD driver pinout or to put the receiver device on the top side or the bottom side of the PCB. The F/S control input selects between a slow CMOS bus output rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher load designs. Two Link Select lines LS0 and LS1 select whether 1, 2, or 3 serial links are used. The RXEN input may be used to put the SN65LVDS314 in a Shutdown mode. The SN65LVDS314 enters an active Standby mode if the common mode voltage of the CLK input becomes shifted to VDDLVDS (e.g., transmitter releases the CLK output into high-impedance). This minimizes power consumption without the need of switching an external control pin. The SN65LVDS314 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS and SubLVDS signals are 2-V tolerant with VDD= 0 V. This feature allows signal powerup before VDDis stabilized.

The SN65LVDS315 is a camera serializer that converts 8-bit parallel camera data into MIPI-CSI1 or SMIA CCP compliant serial signals. The device converts the parallel 8-bit data to two sub-low-voltage differential signaling (SubLVDS) serial data and clock output. Meanwhile the serialized data is presented on the differential serial data output DOUT with a differential clock signal on output CLK. Where The frequency of CLK is 8x DCLK input pixel clock rate. The SN65LVDS315 supports three power modes (Shutdown, standby and active) to conserve power. All CMOS inputs offer failsafe operation to protect the input from damage during power up and to avoid current flow into the device inputs during power up. The core supply of the SN65LVDS315 is 1.8 V. To provide greater flexibility, the camera data inputs support a supply range from 1.8 V to 3.3 V and the device is characterized for operation over ambient air temperatures of –40°C to 85°C. The SN65LVDS315 is a camera serializer that converts 8-bit parallel camera data into MIPI-CSI1 or SMIA CCP compliant serial signals. The device converts the parallel 8-bit data to two sub-low-voltage differential signaling (SubLVDS) serial data and clock output. Meanwhile the serialized data is presented on the differential serial data output DOUT with a differential clock signal on output CLK. Where The frequency of CLK is 8x DCLK input pixel clock rate. The SN65LVDS315 supports three power modes (Shutdown, standby and active) to conserve power. All CMOS inputs offer failsafe operation to protect the input from damage during power up and to avoid current flow into the device inputs during power up. The core supply of the SN65LVDS315 is 1.8 V. To provide greater flexibility, the camera data inputs support a supply range from 1.8 V to 3.3 V and the device is characterized for operation over ambient air temperatures of –40°C to 85°C.

This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers. Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of -4 to 5 V in their SN65LVDS/T33 and SN65LVDS/T34. Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range. The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also available for multidrop or other termination circuits. The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat. The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling. The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, and SN65LVDT9637B are characterized for operation from -40°C to 85°C. This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers. Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of -4 to 5 V in their SN65LVDS/T33 and SN65LVDS/T34. Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range. The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also available for multidrop or other termination circuits. The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat. The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling. The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, and SN65LVDT9637B are characterized for operation from -40°C to 85°C.