| Logic | 4 | Active | The SN65LVDS125A and SN65LVDT125A are 4x4 nonblocking crosspoint switches. Low-voltage differential signaling (LVDS) is used to achieve signaling rates of 1.5 Gbps per channel. Each output driver includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT125A incorporates 110-Ω termination resistors for those applications where board space is a premium.
Designed to support signaling rates up to 1.5 Gbps for OC-12 clocks (622 MHz). The 1.5-Gbps signaling rate allows use in HDTV systems, including SMPTE 292 video applications requiring signaling rates of 1.485 Gbps.
The SN65LVDS125A and SN65LVDT125A are characterized for operation from –40°C to 85°C.
The SN65LVDS125A and SN65LVDT125A are 4x4 nonblocking crosspoint switches. Low-voltage differential signaling (LVDS) is used to achieve signaling rates of 1.5 Gbps per channel. Each output driver includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT125A incorporates 110-Ω termination resistors for those applications where board space is a premium.
Designed to support signaling rates up to 1.5 Gbps for OC-12 clocks (622 MHz). The 1.5-Gbps signaling rate allows use in HDTV systems, including SMPTE 292 video applications requiring signaling rates of 1.485 Gbps.
The SN65LVDS125A and SN65LVDT125A are characterized for operation from –40°C to 85°C. |
| Integrated Circuits (ICs) | 2 | Active | The MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of differential transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher transmission efficiencies than with other existing fixed ratio solutions. Muxlt utilizes the LVDS (TIA/EIA-644) low voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications;The SN65LVDS150 Phase Locked Loop-Frequency Multiplier, The SN65LVDS151 Serializer-Transmitter,andThe SN65LVDS152 Receiver-Deserializer.
The SN65LVDS150 is a PLL based frequency multiplier designed for use with the other members of the MuxIt family of serializers and deserializers. The frequency multiplication ratio is pin selectable over a wide range of values from 4 through 40 to accommodate a broad spectrum of user needs. No external filter components are needed. A PLL lock indicator output is available which may be used to enable link data transfers.
The design of the SN65LVDS150 allows it to be used at either the transmit end or the receive end of the MuxIt serial link. The differential clock reference input (CRI) is driven by the system's parallel data clock when at the source end of the link, or by the link clock when at the destination end of the link. The differential clock reference input may be driven by either an LVDS differential signal, or by a single ended clock of either polarity. For single-ended use the nonclocked input is biased to the logic threshold voltage. A VCC/2 threshold reference, VT, is provided on a pin adjacent the differential CRI pins for convenience when the input is used in a single-ended mode.
The multiplied clock output (MCO) is an LVDS differential signal used to drive the high-speed shift registers in either the SN65LVDS151 serializer-transmitter or the SN65LVDS152 receiver-deserializer. The link clock reference output (LCRO) is an LVDS differential signal provided to the SN65LVDS151 serializer-transmitter for transmission over the link.
An internal power on reset and an enable input (EN) control the operation of the SN65LVDS150. When VCCis below 1.5 V, or when EN is low, the device is in a low power disabled state and the MCO and LCRO differential outputs are in a high-impedance state. When VCCis above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock reference output enable input (LCRO_EN) is used to turn off the LCRO output when it is not being used. A band select input (BSEL) is used to optimize the VCO performance as a function of M-clock frequencies and M multiplier that is being used: The fmaxparameter in the switching characteristic table includes details on the MCO frequency and choices of BSEL and M.
The MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of differential transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher transmission efficiencies than with other existing fixed ratio solutions. Muxlt utilizes the LVDS (TIA/EIA-644) low voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications;The SN65LVDS150 Phase Locked Loop-Frequency Multiplier, The SN65LVDS151 Serializer-Transmitter,andThe SN65LVDS152 Receiver-Deserializer.
The SN65LVDS150 is a PLL based frequency multiplier designed for use with the other members of the MuxIt family of serializers and deserializers. The frequency multiplication ratio is pin selectable over a wide range of values from 4 through 40 to accommodate a broad spectrum of user needs. No external filter components are needed. A PLL lock indicator output is available which may be used to enable link data transfers.
The design of the SN65LVDS150 allows it to be used at either the transmit end or the receive end of the MuxIt serial link. The differential clock reference input (CRI) is driven by the system's parallel data clock when at the source end of the link, or by the link clock when at the destination end of the link. The differential clock reference input may be driven by either an LVDS differential signal, or by a single ended clock of either polarity. For single-ended use the nonclocked input is biased to the logic threshold voltage. A VCC/2 threshold reference, VT, is provided on a pin adjacent the differential CRI pins for convenience when the input is used in a single-ended mode.
The multiplied clock output (MCO) is an LVDS differential signal used to drive the high-speed shift registers in either the SN65LVDS151 serializer-transmitter or the SN65LVDS152 receiver-deserializer. The link clock reference output (LCRO) is an LVDS differential signal provided to the SN65LVDS151 serializer-transmitter for transmission over the link.
An internal power on reset and an enable input (EN) control the operation of the SN65LVDS150. When VCCis below 1.5 V, or when EN is low, the device is in a low power disabled state and the MCO and LCRO differential outputs are in a high-impedance state. When VCCis above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock reference output enable input (LCRO_EN) is used to turn off the LCRO output when it is not being used. A band select input (BSEL) is used to optimize the VCO performance as a function of M-clock frequencies and M multiplier that is being used: The fmaxparameter in the switching characteristic table includes details on the MCO frequency and choices of BSEL and M. |
| Interface | 3 | Active | MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user-selectable and allows for higher transmission efficiencies than with existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152 receiver-deserializer.
The SN65LVDS151 consists of a 10-bit parallel-in/serial-out shift register, three LVDS differential transmission line receivers, a pair of LVDS differential transmission line drivers, plus associated input buffers. It accepts up to 10 bits of user data on parallel data inputs (DI-0 → DI-9) and serializes (multiplexes) the data for transmission over an LVDS transmission line link. Two or more SN65LVDS151 units may be connected in series (cascaded) to accommodate wider parallel data paths for higher serialization values. Data is transmitted over the LVDS serial link at M times the input parallel data clock frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier with configuration pins (M1 → M5). The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier is between 4 and 40.Table 1 shows some of the combinations of LCRI and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.
Data is parallel loaded into the SN65LVDS151 input latches on the first rising edge of the M-clock input (MCI) signal following a rising edge of the link clock reference input (LCRI). The data is read out serially from the SN65LVDS151 shift registers on the rising edges of the M-clock input (MCI). The lowest order bit of parallel input data, DI-0, is output from DO on the third rising edge of MCI following the rising edge of LCRI. The remaining bits of parallel input data, DI-1 → DI-(M-1) are clocked out sequentially, in ascending order, by subsequent MCI rising edges. The link clock output (LCO) signal rising edge is synchronized to the data output (DO) by an internal circuit clocked by MCI. The LCO signal rising edge follows the first rising edge of MCI after the rising edge of LCRI. Examples of operating waveforms for values of M = 4 and M = 10 are provided in Figure 1.
Both the LCRI and MCI signals are intended to be sourced from the SN65LVDS150 MuxIt programmable frequency multiplier. They are carried over LVDS differential connections to minimize skew and jitter. The SN65LVDS151 includes LVDS differential line drivers for both the serialized data output (DO) stream and the link clock output (LCO). The cascade input (CI) is also an LVDS connection, and when it is used it is tied to the DO output of the preceding SN65LVDS151.
An internal power-on reset (POR) and an enable input (EN) control the operation of the SN65LVDS151. When VCCis below 1.5 V, or when EN is low, the device is in a low-power disabled state, and the DO and LCO differential outputs are in a high-impedance state. When VCCis above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock output enable input (LCO_EN) is used to turn off the LCO output when it is not being used. Cascade input enable (CI_EN) is used to turn off the CI input when it is not being used.
Serialized data bits are output from the DO output, starting in ascending order, from parallel input bit DI-0. The number of serialized data bits output per data clock cycle is determined by the multiplexing ratio M. For values of M less than or equal to 10, the cascade input (CI±) is not used, and only the first M parallel input bits (DI-0 thought DI-[M-1]) are used. For values of M greater than 10, all ten parallel input bits (DI-0 though DI-9) are used, and the cascade input is used to shift in the remaining data bits from additional SN65LVDS151 serializers. Table 2 shows which input data bits are used as a function of the multiplier M.
MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user-selectable and allows for higher transmission efficiencies than with existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152 receiver-deserializer.
The SN65LVDS151 consists of a 10-bit parallel-in/serial-out shift register, three LVDS differential transmission line receivers, a pair of LVDS differential transmission line drivers, plus associated input buffers. It accepts up to 10 bits of user data on parallel data inputs (DI-0 → DI-9) and serializes (multiplexes) the data for transmission over an LVDS transmission line link. Two or more SN65LVDS151 units may be connected in series (cascaded) to accommodate wider parallel data paths for higher serialization values. Data is transmitted over the LVDS serial link at M times the input parallel data clock frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier with configuration pins (M1 → M5). The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier is between 4 and 40.Table 1 shows some of the combinations of LCRI and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.
Data is parallel loaded into the SN65LVDS151 input latches on the first rising edge of the M-clock input (MCI) signal following a rising edge of the link clock reference input (LCRI). The data is read out serially from the SN65LVDS151 shift registers on the rising edges of the M-clock input (MCI). The lowest order bit of parallel input data, DI-0, is output from DO on the third rising edge of MCI following the rising edge of LCRI. The remaining bits of parallel input data, DI-1 → DI-(M-1) are clocked out sequentially, in ascending order, by subsequent MCI rising edges. The link clock output (LCO) signal rising edge is synchronized to the data output (DO) by an internal circuit clocked by MCI. The LCO signal rising edge follows the first rising edge of MCI after the rising edge of LCRI. Examples of operating waveforms for values of M = 4 and M = 10 are provided in Figure 1.
Both the LCRI and MCI signals are intended to be sourced from the SN65LVDS150 MuxIt programmable frequency multiplier. They are carried over LVDS differential connections to minimize skew and jitter. The SN65LVDS151 includes LVDS differential line drivers for both the serialized data output (DO) stream and the link clock output (LCO). The cascade input (CI) is also an LVDS connection, and when it is used it is tied to the DO output of the preceding SN65LVDS151.
An internal power-on reset (POR) and an enable input (EN) control the operation of the SN65LVDS151. When VCCis below 1.5 V, or when EN is low, the device is in a low-power disabled state, and the DO and LCO differential outputs are in a high-impedance state. When VCCis above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock output enable input (LCO_EN) is used to turn off the LCO output when it is not being used. Cascade input enable (CI_EN) is used to turn off the CI input when it is not being used.
Serialized data bits are output from the DO output, starting in ascending order, from parallel input bit DI-0. The number of serialized data bits output per data clock cycle is determined by the multiplexing ratio M. For values of M less than or equal to 10, the cascade input (CI±) is not used, and only the first M parallel input bits (DI-0 thought DI-[M-1]) are used. For values of M greater than 10, all ten parallel input bits (DI-0 though DI-9) are used, and the cascade input is used to shift in the remaining data bits from additional SN65LVDS151 serializers. Table 2 shows which input data bits are used as a function of the multiplier M. |
| Integrated Circuits (ICs) | 2 | Active | MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher transmission efficiencies than with other existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152 receiver-deserializer.
The SN65LVDS152 consists of three LVDS differential transmission line receivers, an LVDS differential transmission line driver, a 10-bit serial-in/parallel-out shift register, plus associated input and output buffers. It receives serialized data over an LVDS transmission line link, deserializes (demultiplexes) it, and delivers it on parallel data outputs, DO–0 through DO–9. Data received over the link is clocked at a factor of M times the original parallel data frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed with configuration pins (M1 → M5) on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier. Up to 10 bits of data may be deserialized and output by each SN65LVDS152. Two or more SN65LVDS152 units may be connected in series (cascaded) to accommodate wider parallel data paths for higher serialization values. The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier is between 4 and 40. shows some of the combinations of LCI and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.
Data is serially shifted into the SN65LVDS152 shift register on the falling edges of the M-clock input (MCI). The data is latched out in parallel from the SN65LVDS152 shift register on the second rising edge after the first falling edge of the M-clock following a rising edge of the link clock input (LCI). The SN65LVDS152 includes LVDS differential line receivers for both the serialized link data stream (DI) and link clock (LCI). High-speed signals from the SN65LVDS150 MuxIt programmable frequency multiplier (MCI), plus the input and output for cascaded data (DI, CO) are carried over differential connections to minimize skew and jitter.
The enable input (EN) along with internal power-on reset (POR) controls the outputs. When Vcc is below 1.5 volts, or when EN is low, outputs are disabled. When VCCis above 3 V and EN is high, outputs are enabled and operating to specifications.
Parallel data bits are output from DO-n outputs in an order dependent on the value of the multiplexing ratio (frequency multiplier value) M. For values of M from 4 through 10, the cascade output (CO±) is not used, and only the top M parallel outputs (DO–9 through DO–[10-M]) are used. The data bit output on DO-9 corresponds to the data bit input on DI–[M–1] of the SN65LVDS151 serializer. Likewise, the data bit output on DO-[10-M] will correspond to the data bit input on DI–0 of the SN65LVDS151 serializer.
For values of M greater than 10, the cascade output (CO±) is used to connect multiple SN65LVDS152 deserializers. In this case the higher-order unit(s) output 10 bits each of the highest numbered bits that are input into the SN65LVDS151 serializer(s). The lowest numbered input bits are output on the lowest-order SN65LVDS152 deserializer in descending order from output DO–9. The number of bits is equal to M mod(10). reflects this information, where X = M mod(10)
Additional information on output bit ordering in cascaded applications can be found in the MuxIt Application Report.
MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher transmission efficiencies than with other existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152 receiver-deserializer.
The SN65LVDS152 consists of three LVDS differential transmission line receivers, an LVDS differential transmission line driver, a 10-bit serial-in/parallel-out shift register, plus associated input and output buffers. It receives serialized data over an LVDS transmission line link, deserializes (demultiplexes) it, and delivers it on parallel data outputs, DO–0 through DO–9. Data received over the link is clocked at a factor of M times the original parallel data frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed with configuration pins (M1 → M5) on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier. Up to 10 bits of data may be deserialized and output by each SN65LVDS152. Two or more SN65LVDS152 units may be connected in series (cascaded) to accommodate wider parallel data paths for higher serialization values. The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier is between 4 and 40. shows some of the combinations of LCI and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.
Data is serially shifted into the SN65LVDS152 shift register on the falling edges of the M-clock input (MCI). The data is latched out in parallel from the SN65LVDS152 shift register on the second rising edge after the first falling edge of the M-clock following a rising edge of the link clock input (LCI). The SN65LVDS152 includes LVDS differential line receivers for both the serialized link data stream (DI) and link clock (LCI). High-speed signals from the SN65LVDS150 MuxIt programmable frequency multiplier (MCI), plus the input and output for cascaded data (DI, CO) are carried over differential connections to minimize skew and jitter.
The enable input (EN) along with internal power-on reset (POR) controls the outputs. When Vcc is below 1.5 volts, or when EN is low, outputs are disabled. When VCCis above 3 V and EN is high, outputs are enabled and operating to specifications.
Parallel data bits are output from DO-n outputs in an order dependent on the value of the multiplexing ratio (frequency multiplier value) M. For values of M from 4 through 10, the cascade output (CO±) is not used, and only the top M parallel outputs (DO–9 through DO–[10-M]) are used. The data bit output on DO-9 corresponds to the data bit input on DI–[M–1] of the SN65LVDS151 serializer. Likewise, the data bit output on DO-[10-M] will correspond to the data bit input on DI–0 of the SN65LVDS151 serializer.
For values of M greater than 10, the cascade output (CO±) is used to connect multiple SN65LVDS152 deserializers. In this case the higher-order unit(s) output 10 bits each of the highest numbered bits that are input into the SN65LVDS151 serializer(s). The lowest numbered input bits are output on the lowest-order SN65LVDS152 deserializer in descending order from output DO–9. The number of bits is equal to M mod(10). reflects this information, where X = M mod(10)
Additional information on output bit ordering in cascaded applications can be found in the MuxIt Application Report. |
SN65LVDS162.5-V/3.3-V oscillator gain stage/buffer with enable | Signal Buffers, Repeaters, Splitters | 1 | Active | These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
SN65LVDS172.5-V/3.3-V oscillator gain stage/buffer with enable | Interface | 2 | Active | These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
SN65LVDS179-EPEnhanced product high-speed differential line drivers and receivers | Integrated Circuits (ICs) | 5 | Active | The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-load, and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100-characteristic impedance. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.)
The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state, but rather disconnects the input and reduces the quiescent power used by the device. (For these functions with a high-impedance driver output, see the SN65LVDM series of devices.) All devices are characterized for operation from -55°C to 125°C.
The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-load, and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100-characteristic impedance. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.)
The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state, but rather disconnects the input and reduces the quiescent power used by the device. (For these functions with a high-impedance driver output, see the SN65LVDM series of devices.) All devices are characterized for operation from -55°C to 125°C. |
SN65LVDS182.5-V/3.3-V oscillator gain stage/buffer with enable | Integrated Circuits (ICs) | 1 | Active | These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
SN65LVDS180-Q1Automotive catalog high-speed differential line transceiver | Drivers, Receivers, Transceivers | 7 | Active | The SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-Ω load and receipt of 50-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).
The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state but rather disconnects the input and reduces the quiescent power used by the device. (For these functions with a high-impedance driver output, see the SN65LVDM series of devices.) All devices are characterized for operation from −40°C to 85°C.
The SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-Ω load and receipt of 50-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).
The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state but rather disconnects the input and reduces the quiescent power used by the device. (For these functions with a high-impedance driver output, see the SN65LVDM series of devices.) All devices are characterized for operation from −40°C to 85°C. |
SN65LVDS192.5-V/3.3-V oscillator gain stage/buffer with enable | Integrated Circuits (ICs) | 1 | Active | These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
