Texas Instruments

These 10-bit edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input. A buffered output-enable () input can place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS29821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS29821 is characterized for operation from 0°C to 70°C. These 10-bit edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input. A buffered output-enable () input can place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS29821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS29821 is characterized for operation from 0°C to 70°C.

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs asynchronously when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs, but has no effect on clearing, shifting, or storing data. The SN54ALS299 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS299 is characterized for operation from 0°C to 70°C. These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs asynchronously when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs, but has no effect on clearing, shifting, or storing data. The SN54ALS299 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS299 is characterized for operation from 0°C to 70°C.

These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C. These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C.

The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous functions are executed on the positive-going edge of the clock (CLK) input. The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP\) and enable T (ENT\) are low and ACLR\, SCLR\, andare high. The up/down (U/D\) input controls the direction of the count. These counters count up when U/D\ is high and count down when U/D\ is low. A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of. ENT\ is fed forward to enable the ripple-carry output (RCO\) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum (9 or 15) when counting up. The clocked carry output (CCO\) produces a low-level pulse for a duration equal to that of the low level of the clock whenis low and the counter is enabled (both ENP\ and ENT\ are low); otherwise, CCO\ is high. CCO\ does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connectingor CCO\ of the first counter to ENT\ of the next counter. However, for very high-speed counting,should be used for cascading since CCO\ does not become active until the clock returns to the low level. The SN54ALS569A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C. The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous functions are executed on the positive-going edge of the clock (CLK) input. The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP\) and enable T (ENT\) are low and ACLR\, SCLR\, andare high. The up/down (U/D\) input controls the direction of the count. These counters count up when U/D\ is high and count down when U/D\ is low. A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of. ENT\ is fed forward to enable the ripple-carry output (RCO\) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum (9 or 15) when counting up. The clocked carry output (CCO\) produces a low-level pulse for a duration equal to that of the low level of the clock whenis low and the counter is enabled (both ENP\ and ENT\ are low); otherwise, CCO\ is high. CCO\ does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connectingor CCO\ of the first counter to ENT\ of the next counter. However, for very high-speed counting,should be used for cascading since CCO\ does not become active until the clock returns to the low level. The SN54ALS569A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.

These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, outputs (Q) respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. does not affect internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C. These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, outputs (Q) respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. does not affect internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C.

These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN74ALS575A, SN54AS575, and SN74AS575 may be synchronously cleared by taking the clear () input low. The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS574B, SN54AS574, and SN54AS575 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS574B, SN74ALS575A, SN74AS574, and SN74AS575 are characterized for operation from 0°C to 70°C. These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN74ALS575A, SN54AS575, and SN74AS575 may be synchronously cleared by taking the clear () input low. The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS574B, SN54AS574, and SN54AS575 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS574B, SN74ALS575A, SN74AS574, and SN74AS575 are characterized for operation from 0°C to 70°C.

These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These flip-flops enter data on the low-to-high transition of the clock (CLK) input. The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are disabled. The SN54ALS576B and SN54AS576 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS576B, SN74ALS577A, and SN74AS576 are characterized for operation from 0°C to 70°C. These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These flip-flops enter data on the low-to-high transition of the clock (CLK) input. The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are disabled. The SN54ALS576B and SN54AS576 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS576B, SN74ALS577A, and SN74AS576 are characterized for operation from 0°C to 70°C.

These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, outputs (Q\) respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enableinput can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS580B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS580B and SN74AS580 are characterized for operation from 0°C to 70°C. These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, outputs (Q\) respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enableinput can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS580B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS580B and SN74AS580 are characterized for operation from 0°C to 70°C.

These devices consist of bus-transceiver circuits with 3-state or open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers. Output-enable () and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either or both registers. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data whenis low. In the isolation mode (high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The -1 version of the SN74ALS646A is identical to the standard version, except that the recommended maximum IOLin the -1 version is increased to 48 mA. There are no -1 versions of the SN54ALS646, SN54ALS648, or SN74ALS648A. The SN54ALS646, SN54ALS648, and SN54AS646 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS646A, SN74ALS648A, SN74AS646, and SN74AS648 are characterized for operation from 0°C to 70°C. These devices consist of bus-transceiver circuits with 3-state or open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers. Output-enable () and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either or both registers. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data whenis low. In the isolation mode (high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The -1 version of the SN74ALS646A is identical to the standard version, except that the recommended maximum IOLin the -1 version is increased to 48 mA. There are no -1 versions of the SN54ALS646, SN54ALS648, or SN74ALS648A. The SN54ALS646, SN54ALS648, and SN54AS646 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS646A, SN74ALS648A, SN74AS646, and SN74AS648 are characterized for operation from 0°C to 70°C.

These devices contain six independent 2-input OR drivers. They perform the Boolean functions Y = A + B orin positive logic. The SN54ALS832A and SN54AS832B are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS832A and SN74AS832B are characterized for operation from 0°C to 70°C. These devices contain six independent 2-input OR drivers. They perform the Boolean functions Y = A + B orin positive logic. The SN54ALS832A and SN54AS832B are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS832A and SN74AS832B are characterized for operation from 0°C to 70°C.