NB3W1200L3.3 V 100/133 MHz Differential 1:12 Push-Pull Clock ZDB/Fanout Buffer for PCle | Integrated Circuits (ICs) | 2 | Active | The NB3N1200K and NB3W1200L differential clock buffers areDB1200Z and DB1200ZL compliant and are designed to work inconjunction with a PCIe compliant source clock synthesizer to providepoint−to−point clocks to multiple agents. The device is capable ofdistributing the reference clocks for Intel® QuickPath Interconnect(Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel ScalableMemory Interconnect (Intel SMI) applications. The VCO of thedevice is optimized to support 100 MHz and 133 MHz frequencyoperation. The NB3N1200K and NB3W1200L utilizepseudo−external feedback topology to achieve low input−to outputdelay variation. The NB3N1200K is configured with the HCSL buffertype, while the NB3W1200L is configured with the low−powerNMOS Push−Pull buffer type. |
| Integrated Circuits (ICs) | 1 | Active | |
| Development Boards, Kits, Programmers | 1 | Active | |
NB4L522.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination | Logic | 1 | Active | The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3mm x 3mm 16 pin QFN package. |
| Logic | 1 | Obsolete | |
| Translators, Level Shifters | 1 | Obsolete | |
| Integrated Circuits (ICs) | 1 | Obsolete | |
NB4N441PLL Clock Synthesizer, Multiprotocol, 3.3 V Serial Input, with Differential LVPECL Output | Clock/Timing | 1 | Active | The NB4N441 is a precision clock synthesizer which generates a differential LVPECL clock output frequency from 12.5 MHz to 425 MHz. A Serial Peripheral Interface (SPI) is used to configure the device to produce one of sixteen popular standard protocol output frequencies from a single 27 MHz crystal reference. The NB4N441 also has the added feature of allowing application specific output frequencies from 12.5 MHz to 425 MHz using crystals within the range of 10 MHz to 28 MHz. |
NB4N507APECL Clock Synthesizer, 3.3 V / 5 V, 50 - 200 MHz | Integrated Circuits (ICs) | 3 | Active | The NB4N507A is a precision clock synthesizer which generates a very low jitter differential PECL output clock. It produces a clock output based on an integer multiple of an input reference frequency.The NB4N507A accepts a standard fundamental mode crystal, using Phase-Locked-Loop (PLL) techniques, will produce output clocks up to 200 MHz. In addition, the PLL circuitry will produce a 50% duty cycle square-wave clock output.The NB4N507A can be programmed to generate a selection of input reference frequency multiples. An exact 155.52 MHz output clock can be generated from a 19.44 MHz crystal and the x8 multiplier selection. The NB4N507A is intended for low output jitter clock generation. |
NB4N527STranslator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination | Evaluation and Demonstration Boards and Kits | 3 | Active | NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTMinput signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 Gb/s or 1.25 GHz, respectively.The NB4N527S has a wide input common mode range of GND+50 mV to VCC-50 mV combined with two 50 Ω internal termination resistors is ideal for translating differential or single-ended data or clock signals to 350 mV typical LVDS output levels without use of any additional external components.The device is offered in a small 3 mm x 3 mm QFN-16 package. NB4N527S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements. |
