NB4L52 Series

2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination

Catalog

2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination

Part	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Max Propagation Delay @ V, Max CL	Number of Bits per Element	Output Type	Package / Case	Clock Frequency	Operating Temperature [Max]	Operating Temperature [Min]	Number of Elements	Supplier Device Package	Function	Type	Trigger Type
ON Semiconductor NB4L52MNG	2.375 V	5.5 V	Surface Mount	500 ps	1	Complementary	16-VFQFN Exposed Pad	4 GHz	85 °C	-40 °C	1	16-QFN (3x3)	Reset	D-Type	Negative Edge

Catalog

2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination

Key Features

• Maximum Input Clock Frequency > 4 GHz Typical

• 330 ps Typical Propagation Delay

• 145 ps Typical Rise and Fall Times

• Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical

• Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V

Description

The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3mm x 3mm 16 pin QFN package.