ON Semiconductor

The MC100EP40 is a three-state phase-frequency detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V / 5 V power supply.When Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.When Reference (R) and Feedback (FB) inputs are 80 pS or less in phase difference, the Phase Lock Detect pin will indicate lock by a high state. The VTX(VTR, VTRbar , VTFB, VTFBbar ) pins offer an internal termination network for 50 line impedance environment shown in Figure 2. An external sinking supply of VCC-2 V is required on VTXpin(s). If you short the two differential VTRand VTR(or VTFBand VTFBbar ) together, you provide a 100 termination resistance that is compatible with LVDS signal receiver termination. For more information on termination of logic devices, see AND8020.The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 F capacitor and limit current sourcing or sinkingto 0.5 mA. When not used, VBBshould be left open.For more information on Phase Lock Loop operation, refer to AND8040.Special considerations are required for differential inputs under No Signal conditio

The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE+ 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.The 100 Series contains temperature compensation.

The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEEand the CLKbar input will be biased at VCC/ 2.

The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to VEE) the outputs of the device will remain stable.

The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBBpins are provided.The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBBshould be left open.The device features both individual and common select inputs to address both data path and random logic applications.The 100 Series contains temperature compensation.

The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can also be used as a differential 2:1 multiplexer with SEL0 input selecting between D0 and D1. The fully differential architecture of the EP57 makes it ideal for use in low skew applications such as clock distribution.The SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0).Multiple VBBoutputs are provided. The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBBshould be left open.The 100 Series contains temperature compensation.

The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals. A VBBoutput is provided for interfacing with single ended LVECL or ECL signals at the input. If a single ended input is to be used the VBBoutput should be connected to the D input. The active signal would then drive the D input. When used the VBBoutput should be bypassed to ground by a 0.01 F capacitor. The VBBoutput is designed to act as the switching reference for the EP90 under single ended input switching conditions, as a result this pin can only source/sink up to 0.5mA of current.To accomplish the level translation the EP90 requires three power rails. The VCCsupply should be connected to the positive supply, and the VEEconnected to the negative supply.The 100 Series contains temperature compensation.