MC100EPT20Translator, LVTTL / LVCMOS to Differential LVPECL | Logic | 7 | Active | The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC-8 package and the single gate of the EPT20 makes it ideal for those applications where space, performance, and low power are at a premium. |
MC100EPT21Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator | Translators, Level Shifters | 5 | Active | The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.The VBBoutput allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, VBBoutput tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, VBBoutput is connected through a resistor to each input pin. If used, the VBBpin should be bypassed to VCCvia a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBBfor a single-ended direct connection. |
MC100EPT23Translator, Dual Differential LVPECL to LVTTL | Logic | 3 | Active | The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applications which require the translation of a clock and a data signal.The EPT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBBreference, the EPT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100EPT23 can accept any standard differential LVPECL input referenced from a VCCof +3.3V. |
MC100EPT25Translator, Differential LVECL / ECL to LVTTL | Translators, Level Shifters | 2 | Active | The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal.The VBBoutput allows the EPT25 to also be used in a single-ended input mode. In this mode the VBBoutput is tied to the D input for a inverting buffer or the Dbar input for a non-inverting buffer. If used, the VBBpin should be bypassed to ground with at least a 0.01 µF capacitor. |
MC100EPT26Translator, 1:2 Fanout Differential LVPECL / LVDS to LVTTL | Translators, Level Shifters | 5 | Active | The MC100EPT26 is a 1:2 Fanout Differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board.The VBBoutput allows the EPT26 to be used in a single-ended input mode. In this mode the VBBoutput is tied to the D0bar input for a non-inverting buffer or the D0 input for an inverting buffer. If used, the VBBpin should be bypassed to ground via a 0.01 uF capacitator. |
| Translators, Level Shifters | 5 | Active | The MC100EPT622 is a 10-Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used, only +3.3 V and ground are required. The device has an OR-ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel-to-channel skew. |
| Application Specific | 8 | Obsolete | |
| Gates and Inverters - Multi-Function, Configurable | 3 | Active | The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally suited for those applications which require the ultimate in AC performance at low voltage power supplies.Because a negative 2-input NAND is equivalent to a 2-input OR function, the differential inputs and outputs of the device allows the LVEL05 to also be used as a 2-input differential OR/NOR gate. |
| Specialty Logic | 4 | Active | The MC100LVEL16 is a differential receiver. The device is functionally equivalent to the EL16 device, operating from a 3.3 V supply. The LVEL16 exhibits a wider VIHCMR range than its EL16 counterpart. With output transition times and propagation delays comparable to the EL16 the LVEL16 is ideally suited for interfacing with high frequency sources at 3.3 V supplies. Under open input conditions, the Q input will be pulled down to VEEand the Qbar input will be biased to VCC/2. This condition will force the Q output low. The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. |
| Integrated Circuits (ICs) | 2 | Active | The MC100LVEL17 is a 3.3 V ECL, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a -3.3 V or +3.3 V supply voltage.Under open input conditions, the Dbar input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability.The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBBshould be left open. |