MC100EP451 Series

3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset

Catalog

3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset

Part	Number of Bits per Element	Number of Elements	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Quiescent (Iq)	Operating Temperature [Max]	Operating Temperature [Min]	Clock Frequency	Output Type	Type	Mounting Type	Trigger Type	Supplier Device Package
ON Semiconductor MC100EP451FAG	6	1	32-LQFP	-5.5 V	-3 V	135 mA	85 °C	-40 °C	3 GHz	Complementary	D-Type	Surface Mount	Positive Edge	32-LQFP (7x7)
ON Semiconductor MC100EP451MNG	6	1	32-VFQFN Exposed Pad	-5.5 V	-3 V	135 mA	85 °C	-40 °C	3 GHz	Complementary	D-Type	Surface Mount	Positive Edge	32-QFN (5x5)
ON Semiconductor MC100EP451FAR2G	6	1	32-LQFP	-5.5 V	-3 V	135 mA	85 °C	-40 °C	3 GHz	Complementary	D-Type	Surface Mount	Positive Edge	32-LQFP (7x7)
ON Semiconductor MC100EP451FAR2	6	1	32-LQFP	5.5 V	3 V	135 mA	85 °C	-40 °C	3 GHz	Complementary	D-Type	Surface Mount	Positive Edge	32-LQFP (7x7)

Catalog

3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset

Key Features

• 450 ps Typical Propagation Delay

• Maximum Frequency > 3.0 GHz Typical

• Asynchronous Master Reset

• 20 ps Skew Within Device, 35 ps Skew Device-To-Device

• PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V

• NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Pb-Free Packages are Available

Description

The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE+ 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.The 100 Series contains temperature compensation.