ON Semiconductor

The MC100LVEL29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100LVEL29 is pin and functionally equivalent to the MC100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEEand the Dbar input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBBshould be left open.

The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3V VCC.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEEand the CLKbar input will be biased at VCC/2.

The MC100LVEL91 is a triple LVPECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them to differential -3.3 V to -5.0 V ECL output signals. (For translation from 5.0 V PECL to -5 V ECL output, see MC100EL91.)To accomplish the level translation the LVEL91 requires three power rails. The VCCsupply should be connected to the positive supply, and the VEEpin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both VEEand VCCshould be bypassed to ground via 0.01 µF capacitors.Under open input conditions, the Dbar input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a low, ensuring stability.The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBBshould be left open.

The MC100LVEL92 is a triple PECL input to LVPECL output translator. The device receives standard PECL signals and translates them to differential LVPECL output signals.To accomplish the PECL to LVPECL level translation, the MC100LVEL92 requires three power rails. The VCC supply is to be connected to the standard 5 V PECL supply, the LVCC supply is to be connected to the 3.3 V LVPECL supply, and Ground is connected to the system ground plane. Both the VCCand LVCC should be bypassed to ground with 0.01 F capacitors.The PECL VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBBshould be left open.

The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the LVELT22 makes it ideal for applications which require the translation of a clock and a data signal.

The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock and a data signal.The LVELT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBBreference, the LVELT23 does not require both ECL standard versions. The LVPECL inputs are differential; there is no specified difference between the differential input 10H and 100K standards. Therefore, the MC100LVELT23 can accept any standard differential LVPECL input referenced from a VCCof 3.3V.

The MC100LVEP05 is a 2-input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for low voltage applications requiring the fastest AC performance available. The 100 Series contains temperature compensation.