MC100EP52 Series

ECL Differential Clock/Data D Flip-Flop

Catalog

ECL Differential Clock/Data D Flip-Flop

Part	Package / Case	Package / Case [custom]	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Output Type	Supplier Device Package	Function	Current - Quiescent (Iq)	Mounting Type	Clock Frequency	Number of Elements	Operating Temperature [Max]	Operating Temperature [Min]	Number of Bits per Element	Trigger Type	Type
ON Semiconductor MC100EP52DTG	8-MSOP 8-TSSOP	0.118 in	3 mm	-5.5 V	-3 V	Complementary	8-TSSOP	Standard	45 mA	Surface Mount	3 GHz	1	85 °C	-40 °C	1	Negative Positive	D-Type

Catalog

ECL Differential Clock/Data D Flip-Flop

Key Features

• 330ps Typical Propagation Delay

• Maximum Frequency > 4 GHz Typical

• PECL Mode: VCC= 3.0 V to 5.5 V with VEE= 0 V

• NECL Mode: VCC= 0 V with VEE= -3.0 V to -5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Q Output will default LOW with inputs open or at VEE

• Pb-Free Packages are Available

Description

The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to VEE) the outputs of the device will remain stable.