MC100EP51 Series

ECL D Flip-Flop with Reset and Differential Clock

Catalog

ECL D Flip-Flop with Reset and Differential Clock

Part	Package / Case	Package / Case [custom]	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Clock Frequency	Type	Number of Bits per Element	Number of Elements	Mounting Type	Current - Quiescent (Iq)	Supplier Device Package	Output Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Trigger Type	Function	Package / Case [y]	Package / Case [x]
ON Semiconductor MC100EP51DTR2	8-MSOP 8-TSSOP	0.118 in	3 mm	85 °C	-40 °C	3 GHz	D-Type	1	1	Surface Mount	45 mA	8-TSSOP	Complementary	-5.5 V	-3 V	Negative Positive	Reset
ON Semiconductor MC100EP51DG	8-SOIC			85 °C	-40 °C	3 GHz	D-Type	1	1	Surface Mount	45 mA	8-SOIC	Complementary	-5.5 V	-3 V	Negative Positive	Reset	3.9 mm	0.154 in

Catalog

ECL D Flip-Flop with Reset and Differential Clock

Key Features

• 350ps Typical Propagation Delay

• Maximum Frequency > 3 Ghz Typical

• PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V

• NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Pb-Free Packages are Available

Description

The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEEand the CLKbar input will be biased at VCC/ 2.