Microchip Technology

The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350ps, the device acts as a zero delay buffer.

The PL123-05/-09 (-05H/-09H for High Drive) are high performance, low skew, low jitter zero delay buffers designed to distribute high speed clocks. They have one (PL123-05) or two (PL123-09) low-skew output banks, of 4 outputs each, that are synchronized with the input. The PL123-09 allows control of the banks of outputs by using the S1 and S2 inputs as shown in the Selector Definition table on page 2 of the datasheet.The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin.These parts are not intended for 5V input-tolerant applications.

The PL133-37 is an advanced inverting fanout buffer design for high performance, low-power, small form-factor applications. The PL133-37 accepts a LVCMOS or a Sine Wave reference clock input of 1MHz to 150MHz and produces three outputs of the same frequency. Reference clock inputs may be LVCMOS or sine-wave signals (the inputs are internally AC-coupled so no external components required). Offered in a small 3 x 3mm SOT23, the PL133-37 offers the best phase noise and jitter performance and lowest power con-consumption of any comparable IC.

The PL133-97 is an advanced fanout buffer design for high performance, low-power, small form factor applications. The PL133-97 accepts a reference clock input from DC to 150 MHz and provides 9 outputs of the same frequency.The PL133-97 is offered in a QFN-16L 3mm x 3mm package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC. The PL133-97 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled.

The PL135-67 is an advanced oscillator fanout buffer design for high performance, low-power, small form-factor applications. The PL135-67 accepts a fundamental input crystal of 10MHz to 40MHz and produces six outputs of the same frequency, two with their own Output Enable functions.Offered in a small 3 x 3mm QFN or TSSOP package, the PL135-67 offers the best phase noise and jitter performance and lowest power consumption of any comparable IC.

The PL138-48 family is a high performance low-cost 1:4 outputs Differential LVPECL fanout buffer.The family of Differential LVPECL buffers are designed to operate from a single power supply of 2.5V±5% or 3.3V±10%. The differential input pairs are designed to accept most standard input signal levels, using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed for part-to-part or lot-to lot skew.Designed to fit in a small form-factor package, PL138 family offers up to 1GHz of output operation with very low-power consumption, and lowest additive jitter of any comparable device. The Output Enable feature, when activated, allows the IC to consume less than 10µA of current.