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Integrated Circuits (ICs)

SN74LV573APW

Obsolete
Texas Instruments

2V~5.5V D-TYPE LOCKING DEVICE 1NS TSSOP-20 LATCHES ROHS

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Product Image
Integrated Circuits (ICs)

SN74LV573APW

Obsolete
Texas Instruments

2V~5.5V D-TYPE LOCKING DEVICE 1NS TSSOP-20 LATCHES ROHS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LV573APW
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low [custom]16 mA
Current - Output High, Low [custom]16 mA
Delay Time - Propagation1 ns
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case20-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package20-TSSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.18
10$ 1.05
LCSCN/A 1$ 0.00
Texas InstrumentsTUBE 1$ 0.87
100$ 0.67
250$ 0.49
1000$ 0.35

Description

General part information

SN74LV573AT Series

The SN74LV573AT is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

To ensure the high-impedance state during power up or power down,OEshall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.