SN74LV573AT Series

Octal Transparent D-Type Latches With 3-State Outputs

Catalog

Octal Transparent D-Type Latches With 3-State Outputs

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Max]	Voltage - Supply [Min]	Independent Circuits	Logic Type	Package / Case	Package / Case [y]	Package / Case [y]	Supplier Device Package	Output Type	Mounting Type	Delay Time - Propagation	Operating Temperature [Max]	Operating Temperature [Min]	Circuit [custom]	Circuit [custom]	Package / Case [x]	Package / Case	Package / Case
Texas Instruments SN74LV573ATDW	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	20-SOIC	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8
Texas Instruments SN74LV573ADW	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	20-SOIC	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8
Texas Instruments SN74LV573ARGYRG4	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-VFQFN Exposed Pad			20-VQFN (3.5x4.5)	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8
Texas Instruments SN74LV573APW	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-TSSOP	4.4 mm		20-TSSOP	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8	0.173 in
Texas Instruments SN74LV573ATNS	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-SOIC			20-SO	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8		0.209 "	5.3 mm
Texas Instruments SN74LV573ADBRG4	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-SSOP			20-SSOP	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8
Texas Instruments SN74LV573APWR	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-TSSOP	4.4 mm		20-TSSOP	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8	0.173 in
Texas Instruments SN74LV573ATNSRE4	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-SOIC			20-SO	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8		0.209 "	5.3 mm
Texas Instruments SN74LV573ATDBRE4	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-SSOP			20-SSOP	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8
Texas Instruments SN74LV573ADBR	16 mA	16 mA	5.5 V	2 V	1	D-Type Transparent Latch	20-SSOP			20-SSOP	Tri-State	Surface Mount	1 ns	85 °C	-40 °C	8	8

Catalog

Octal Transparent D-Type Latches With 3-State Outputs

Key Features

• Inputs Are TTL-Voltage Compatible4.5-V to 5.5-V VCCOperationTypical tpd= 5.1 ns at 5 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 5 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2.3 V at VCC= 5 V, TA= 25°CSupports Mixed-Mode Voltage Operation on All PortsIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Inputs Are TTL-Voltage Compatible4.5-V to 5.5-V VCCOperationTypical tpd= 5.1 ns at 5 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 5 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2.3 V at VCC= 5 V, TA= 25°CSupports Mixed-Mode Voltage Operation on All PortsIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

The SN74LV573AT is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down,OEshall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OEdoes not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74LV573AT is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down,OEshall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OEdoes not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.