Specification	SN74LVTH273PW

Clock Frequency	150 MHz
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Current - Quiescent (Iq)	190 çA
Input Capacitance	4 pF
Max Propagation Delay @ V, Max CL	4.9 ns
Mounting Type	Surface Mount
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Non-Inverted
Package / Case	20-TSSOP
Package / Case [x]	0.173 in
Package / Case [y]	4.4 mm
Supplier Device Package	20-TSSOP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

SN74LVTH273-EP Series

Enhanced Product 3.3-V Abt Octal D-Type Flip-Flops With Clear

Part	Input Capacitance	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Clock Frequency	Type	Current - Quiescent (Iq)	Output Type	Number of Elements	Max Propagation Delay @ V, Max CL	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Mounting Type	Package / Case	Package / Case [y]	Package / Case [y]	Trigger Type	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case	Package / Case [x]
Texas Instruments SN74LVTH273DWRE4	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-SOIC	Surface Mount	20-SOIC	0.295 in	7.5 mm	Positive Edge
Texas Instruments SN74LVTH273DWRG4	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-SOIC	Surface Mount	20-SOIC	0.295 in	7.5 mm	Positive Edge
Texas Instruments SN74LVTH273MNSREP	4 pF	64 mA	32 mA	8			150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-SO	Surface Mount	20-SOIC			Positive Edge	125 °C	-55 °C	0.209 "	5.3 mm
Texas Instruments SN74LVTH273PW	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-TSSOP	Surface Mount	20-TSSOP	4.4 mm		Positive Edge					0.173 in
Texas Instruments SN74LVTH273PWR	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-TSSOP	Surface Mount	20-TSSOP	4.4 mm		Positive Edge					0.173 in
Texas Instruments SN74LVTH273IPWREP	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-TSSOP	Surface Mount	20-TSSOP	4.4 mm		Positive Edge					0.173 in
Texas Instruments SN74LVTH273NSR	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-SO	Surface Mount	20-SOIC			Positive Edge			0.209 "	5.3 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 0.67
		10	$ 0.60
		70	$ 0.57
		140	$ 0.47
		280	$ 0.44
		560	$ 0.39
		1050	$ 0.36
Texas Instruments	TUBE	1	$ 0.71
		100	$ 0.55
		250	$ 0.40
		1000	$ 0.29

Description

General part information

SN74LVTH273-EP Series

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Documents

Technical documentation and resources

Datasheet

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

SN74LVTH273PW

Deep-Dive with AI

SN74LVTH273PW

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Technical Specifications

SN74LVTH273-EP Series

Pricing

Description

SN74LVTH273-EP Series

Documents

Datasheet

Implications of Slow or Floating CMOS Inputs (Rev. E)

TI IBIS File Creation, Validation, and Distribution Processes

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

Live Insertion

Understanding Advanced Bus-Interface Products Design Guide

LOGIC Pocket Data Book (Rev. B)

Advanced Bus Interface Logic Selection Guide

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

LVT Family Characteristics (Rev. A)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

LVT-to-LVTH Conversion

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Power-Up Behavior of Clocked Devices (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

Logic Guide (Rev. AB)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

SN74LVTH273-EP Series